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參數(shù)資料
| 型號： | 9412AVK |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 14 X 14 MM, 2 MM HEIGHT, PLASTIC, MS-022, MQFP-80 |
| 文件頁數(shù)： | 94/126頁 |
| 文件大?。?/td> | 1673K |
| 代理商： | 9412AVK |
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DATA SHEET
Micronas
Aug. 16, 2004; 6251-552-1DS
7
2. Functional Description
All I2C bus registers mentioned are printed in bold and
italics (e.g. YCDEL).
2.1. CVBS Front-end
The CVBS front-end consists of the color decoding cir-
cuit itself, a sync processing circuit for generation of H/
V signals out of the CVBS signal, and the luminance
processing. The main task of the luminance process-
ing is to remove the color carrier by means of a notch
filter. For PAL and SECAM operation a baseband delay
line is used for U and V signals. This can be used as
comb filter in NTSC operation (only for chrominance).
The RGB input can either be used as an overlay for the
CVBS channel (RGB+FBL) or as a full master channel
(RGB+H/V). The overlay is done by means of a soft-
mix and can be used e.g. for ‘SCART’ connector. This
block contains a matrix (for RGB signals) which is
switched off for YUV (e.g. YPbPr) input signals. A CBS
(contrast, brightness, saturation) control makes the
input signal adjustable.
2.1.1. Source Select
Fig. 2–1 shows the analog front-end. The analog
CVBS signal can be fed to the inputs CVBS1...7 of
VSP 94x2A (amplitude 0.5...1.5 Vpp). One signal is
selected via CVBSEL1 and fed to the first ADC. A sec-
ond signal is selected via CVBSEL2 and fed to the
other ADC. CVBS4&5 or CVBS6&7 are intended to be
use as separate Y/C inputs (YCSEL). After clamping
to the back porch both signals are AD-converted with
an amplitude resolution of 9 bit. The AD conversion is
done using a 20.25 MHz freerunning stable crystal
clock. Before the A to D conversion the signals are
lowpass filtered to avoid antialias effects. Three inputs
can
be
looped
back
to
output
CVBSO1-3
(CVBOSEL1, CVBOSEL2, CVBOSEL3). A signal
addition is performed to output a CVBS signal even
when separate Y/C signals are used at input. Inputs
that are not used are roughly clamped to fit in the
allowed voltage region. For stand-by operation (power-
down mode), A/D and D/A converter are switched off
by STANDBY keeping the source-selector operational.
2.1.2. Signal Levels and Gain Control
To adjust to different CVBS input voltages a digitally
working automatic gain control is implemented. Input
voltages in the range between 0.6 to 1.8 Vpp can be
applied to the CVBS inputs.
For best signal-to-noise ratio the maximum available
CVBS amplitude is recommended.
The AGC behavior can be chosen from four possible
modes (AGCMD) (see Table 2–1).
Fig. 2–1: Input Selection
Table 2–1: AGC Modes
AGCMD
AGC Operation Mode
00
AGC uses the height of the sync pulse
as a reference and additionally reduces
amplification when ADC overflows
01
AGC uses the height of the sync pulse
as a reference
10
AGC uses only ADC overflows
11
AGC is disabled and the ADC fits to the
values given in AGCADJ1
CVBS 1
CVBS 2
CVBS 3
CVBS 4 / Y1
CVBS 5 / C1
CVBS 6 / Y2
CVBS 7 / C2
C
1
/
9
1
/
9
1
/
9
1
/
9
1
/
9
Filter
C
Buffer
ADC_CVBS1
ADC_CVBS2
CVBSO1
CVBSO2
CVBSO3
Clamping pulse of ADC_CVBS1
or ADC_CVBS2.
Shifting of signal to required
input voltage range for
CVBSO1..3
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