參數(shù)資料
型號(hào)： 9412AVK
廠(chǎng)商： MICRONAS SEMICONDUCTOR HOLDING AG
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： 14 X 14 MM, 2 MM HEIGHT, PLASTIC, MS-022, MQFP-80
文件頁(yè)數(shù)： 55/126頁(yè)
文件大?。?/td> 1673K
代理商： 9412AVK
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DATA SHEET
34
Aug. 16, 2004; 6251-552-1DS
Micronas
3. I2C Bus Interface
3.1. I2C Bus Slave Address
When pin 19 (adr/tdi) is connected to Vss, the
VSP 94x2A reacts on the first I2C address (B0h for
write access and B1h for read access). The second
address (B2h and B3h) is active, when pin 19 is con-
nected to Vdd.
3.1.1. I2C Bus Format
The VSP 94x2A I2C bus interface acts as a slave
receiver and a slave transmitter and provides two dif-
ferent access modes (write, read). All modes run with
a subaddress auto increment. The interface supports
the normal 100 kHz transmission speed as well as the
high speed 400 kHz transmission.
The transmitted data is internally stored in registers.
The registers are located in four different clock
domains. The Table 3–5 on page 35 shows the four
different clock domains of the VSP 94x2A. The clock
domains are called CP - CVBS processing block
(20.25 MHz domain, clkf20), FP - Front end processing
block (40.5 MHz domain, clkf40), BP - Back end pro-
cessing block (36.0 MHz domain, clkb36) and PP -
PLL processing block (36.0 MHz domain, clkf36).
The registers themselves are grouped in an I2C bus
interface block, one in each domain. The transmitted
data is received by the I2C bus kernel. The I2C bus ker-
nel itself is located in the CP domain. This means that
the working frequency is 20.25 MHz. The data is trans-
mitted to the I2C bus interface blocks via an internal
serial bus.
For the write process, the I2C bus master has to write
a ‘don’t care’ byte to the subaddress FFh (store com-
mand). This makes the register values available to the
four I2C bus interface blocks (except for the not-take-
over registers, which are used immediately).
In order to have a defined time step for the several
blocks in the different domains, the data are made
valid with internal V-syncs, depending on the different
clock domains.
The subaddresses, where the data are made valid with
the V-sync signal of the 20.25 MHz domain are indi-
cated in the overview of the subaddresses with “V20“.
The others are called “V40”, “V36F” and “V36B”
accordingly.
S: Start condition
SR: Repeated Start condition
A: Acknowledge
P: Stop condition
NA: Not Acknowledge
Table 3–1: I2C bus slave addresses B0h and B1h
Write Address1: B0h
Read Address1: B1h
10 1100 00
10 1100 01
Table 3–2: I2C bus slave addresses B2h and B3h
Write Address2: B2h
Read Address2: B3h
10 1100 10
10 1100 11
Table 3–3: Write
S
1
0
1100
x
0
A
Subaddress
A
Data Byte
A
*****
A
P
Table 3–4: Read
S
1
01
10
0
x
0
A
Suba
dd
re
ss
A
SR
1
01
10
0
x
1
A
Da
ta
Byt
e
A
Da
ta
Byt
e
NA
P
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