參數(shù)資料
型號: 954101DGLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 0.240 INCH, 0.020 INCH PITCH, GREEN, MO-153, TSSOP-56
文件頁數(shù): 5/21頁
文件大?。?/td> 251K
代理商: 954101DGLFT
13
Integrated
Circuit
Systems, Inc.
ICS954101
0815F—08/15/05
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
1
Bit 6
DOT_96MHz
Driven in PD
RW
Driven
Hi-Z
1
Bit 5
PCI_F2
RW
Free-Running
Stoppable
1
Bit 4
PCI_F1
RW
Free-Running
Stoppable
1
Bit 3
PCI_F0
RW
Free-Running
Stoppable
1
Bit 2
1
Bit 1
1
Bit 0
1
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SRC Stop Drive Mode
Drive Mode in
PCI_Stop
RW
Driven
Hi-Z
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
SRC PD Drive Mode
Drive Mode in PD
RW
Driven
Hi-Z
0
Bit 2
CPUCLK_ITP
Drive Mode in PD
RW
Driven
Hi-Z
0
Bit 1
CPUCLK1
Drive mode in PD
RW
Driven
Hi-Z
0
Bit 0
CPUCLK0
Drive mode in PD
RW
Driven
Hi-Z
0
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
Test Mode Selection
Test Mode
Selection
RW
Hi-Z
REF/N
0
Bit 6
Test Clock Mode Entry
Test Mode
RW
Disable
Enable
0
Bit 5
0
Bit 4
REFOUT Strength
Strength Prog
RW
1X
2X
1
Bit 3
PCI/SRC_STOP
Stop all PCI and
SRC clocks
RW
Enabled, all
stoppable PCI
and SRC
clocks are
stopped.
Disabled, all
stoppable PCI
and SRC clocks
are running
1
Bit 2
FS_C
readback
R
-
LATCHED
Bit 1
FS_B
readback
R
-
LATCHED
Bit 0
FS_A
readback
R
-
LATCHED
I
2C Table: Vendor & Revision ID Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
RID3
R
-
0
Bit 6
RID2
R
-
0
Bit 5
RID1
R
-
0
Bit 4
RID0
R
-
0
Bit 3
VID3
R
-
0
Bit 2
VID2
R
-
0
Bit 1
VID1
R
-
0
Bit 0
VID0
R
-
1
-
RESERVED
-
VENDOR ID
-
Byte 7
-
REVISION ID
RESERVED
-
40,41
43,44
52
-
17,18,19,20,22,23,
24,25,26,27,30,31,
32,33,35,36
54,55,56,3,4,5,8,9,
10
19,20,22,23,
24,25,26,27,30,31,
32,33,35,36
35,36
RESERVED
10
9
8
RESERVED
Free-Running
Control
not affected by
RESERVED
Byte 4
-
Byte 5
Byte 6
19,20,22,23,
24,25,26,27,30,31,
32,33,35,36
14,15
-
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