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參數(shù)資料
| 型號： | 97042-99 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 300 MHz, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 456K |
| 代理商： | 97042-99 |
Document No. 70-0236-05
│ www.psemi.com
Page 1 of 11
2007-2011 Peregrine Semiconductor Corp. All rights reserved.
Figure 1. Block Diagram
F
IN
Prescaler
10 / 11
Main
Counter
20-Bit
Frequency
Register
M(8:0)
A(3:0)
R(5:0)
19*
20
R Counter
F
R
Phase
Detector
6
13
Serial
Control
PD_U
PD_D
3
MSEL
f
p
f
c
Direct
Control
* prescaler bypass not available in Direct mode
LD
Cext
Product Specification
PE97042
Features
3.5 GHz UltraCMOS Integer-N PLL
Rad Hard for Space Applications
Low Power: 45 mA Typical
3.5 GHz operation
÷10/11 dual modulus prescaler
Phase detector output
Serial or direct hardwired mode
Ultra-Low Phase Noise: -216 dBc/Hz
SEU < 10-9 errors / bit-day
100 Krad (Si) total dose
Easily modified to be pin compatible
with the PE9704, packaged in a 44-lead
CQFJ (reference application note AN23
at www.psemi.com)
Peregrine’s PE97042 is a high-performance integer-N PLL
capable of frequency synthesis up to 3.5 GHz. The device
is designed for superior phase noise performance while
providing an order of magnitude reduction in current
consumption, when compared with existing commercial
space PLLs.
The PE97042 features a ÷10/11 dual modulus prescaler,
counters, and a phase comparator as shown in Figure 1.
Counter values are programmable through a serial or direct
hardwired mode.
The PE97042 is optimized for commercial space
applications. Single Event Latch up (SEL) is physically
impossible and Single Event Upset (SEU) is better than 10-9
errors per bit / day. It is manufactured on Peregrine’s
UltraCMOS process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering
excellent RF performance and intrinsic radiation tolerance.
Product Description
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