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參數資料
| 型號： | 97042-99 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 300 MHz, UUC |
| 封裝： | DIE |
| 文件頁數： | 2/11頁 |
| 文件大?。?/td> | 456K |
| 代理商： | 97042-99 |
Product Specification
PE97042
Page 10 of 11
2007-2011 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0236-05
│ UltraCMOS RFIC Solutions
Figure 9. Serial Interface Mode Timing Diagram
t
DHLD
t
DSU
t
ClkH
t
ClkL
t
CWR
t
PW
t
WRC
t
EC
t
CE
E_WR
DATA
CLOCK
S_WR
Software tools for designing the active loop filter
can be found at Peregrine’s web site:
www.psemi.com.
Lock Detect Output
A lock detect signal is provided at pin LD, via the
pin CEXT (see Figure 1). CEXT is the logical “NAND”
of PD_
U and PD_D waveforms, driven through a
series 2 k
resistor. Connecting C
EXT to an
external shunt capacitor provides integration of
this signal.
The CEXT signal is then sent to the LD pin through
an internal inverting comparator with an open
drain output. Thus LD is an “AND” function of
PD_
U and PD_D.
Enhancement Register
The functions of the enhancement register bits are shown below. All bits are active high. Operation is
undefined if more than one output is sent to DOUT.
Table 9. Enhancement Register Bit Functionality
Note: 1. Program to 0
Phase Detector Outputs
The phase detector is triggered by rising edges
from the main counter (fp) and the reference
counter (fc). It has two outputs, PD_U, and PD_D.
If the divided VCO leads the divided reference in
phase or frequency (fp leads fc), PD_D pulses
“l(fā)ow”. If the divided reference leads the divided
VCO in phase or frequency (fc leads fp), PD_U
pulses “l(fā)ow”. The width of either pulse is directly
proportional to phase offset between the two input
signals, fp and fc. The phase detector gain is 430
mV/radian.
PD_U and PD_D are designed to drive an active
loop filter which controls the VCO tune voltage.
PD_U pulses result in an increase in VCO
frequency and
PD_D results in a decrease in VCO
frequency.
Bit Function
Description
Bit 0
Reserved1
Bit 1
Reserved1
Bit 2
fp output
Drives the M counter output onto the DOUT output.
Bit 3
Power down
Power down of all functions except programming interface.
Bit 4
Counter load
Immediate and continuous load of counter programming.
Bit 5
MSEL output
Drives the internal dual modulus prescaler modulus select (MSEL) onto the DOUT output.
Bit 6
fc output
Drives the R counter output onto the DOUT output
Bit 7
PB
Allows Fin to bypass the 10/11 prescaler
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