- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25566 > 9FGP202AKLFT (INTEGRATED DEVICE TECHNOLOGY INC) 33.33 MHz, OTHER CLOCK GENERATOR, PQCC40 PDF資料下載
參數(shù)資料
| 型號： | 9FGP202AKLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 33.33 MHz, OTHER CLOCK GENERATOR, PQCC40 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MLF-40 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 137K |
| 代理商： | 9FGP202AKLFT |
7
Integrated
Circuit
Systems, Inc.
ICS9FGP202A
1339C—09/14/09
Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
3.3V Supply Voltage
VDDxxx
-
GND - 0.5
3.3V
GND + 4.5
V
1
Maximum difference across all
VDD pins
VDDdelta
-
0.5
V
1
Storage Temperature
Ts
-
-65
150
°C
1
Ambient Operating Temp
Tambient
-
070
°C
1
Junction Temperature
Tj
-
125
°C
1
Input ESD protection HBM
ESD prot
-
2000
V
1
1Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
Notes
Input High Voltage
V
IH
3.3 V +/-5%
2
V
DD + 0.3
V
1
Input Low Voltage
V
IL
3.3 V +/-5%
V
SS - 0.3
0.8
V
1
Input High Current
I
IH
V
IN = VDD
-5
5
uA
1
I
IL1
V
IN = 0 V; Inputs with no pull-up
resistors
-5
uA
1
I
IL2
V
IN = 0 V; Inputs with pull-up
resistors
-200
uA
1
Low Threshold Input-
High Voltage
V
IH_FS
3.3 V +/-5%
0.7
V
DD + 0.3
V
1
Low Threshold Input-
Low Voltage
V
IL_FS
3.3 V +/-5%
V
SS - 0.3
0.35
V
1
Operating Current
I
DD3.3OP
all outputs driven
200
mA
1
all diff pairs driven
30
mA
1
all differential pairs tri-stated
8
mA
1
Input Frequency
F
i
V
DD = 3.3 V
25.00000
MHz
2
Pin Inductance
L
pin
7nH
C
IN
Logic Inputs
4
pF
1
C
OUT
Output pin capacitance
5
pF
1
C
INX
X1 & X2 pins
5
pF
1
Clk Stabilization
T
STAB
From VDD Power-Up or de-
assertion of PD to 1st clock
2.5
ms
1
Modulation Frequency
Triangular Modulation
30
33
kHz
1
Tdrive_PD
CPU output enable after
PD de-assertion
300
us
1
Tfall_PD
PD fall time of
5
ns
1
Trise_PD
PD rise time of
5
ns
1
SMBus Voltage
V
DD
2.7
5.5
V
1
Low-level Output Voltage
V
OL
@ I
PULLUP
0.4
V
1
Current sinking at
V
OL = 0.4 V
I
PULLUP
4mA
1
SCLK/SDATA
Clock/Data Rise Time
T
RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
T
FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1Guaranteed by design and characterization, not 100% tested in production.
2 Input frequency should be measured at the REF pin and tuned to ideal 25.00MHz to meet ppm frequency accuracy on PLL outputs.
Input Low Current
Powerdown Current
I
DD3.3PD
Input Capacitance
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9G100 | ACTIVE DELAY LINE, TRUE OUTPUT, CDIP4 |
| 9G125S | ACTIVE DELAY LINE, TRUE OUTPUT, CDIP4 |
| 9G125 | ACTIVE DELAY LINE, TRUE OUTPUT, CDIP4 |
| 9G150 | ACTIVE DELAY LINE, TRUE OUTPUT, CDIP4 |
| 9G35 | ACTIVE DELAY LINE, TRUE OUTPUT, CDIP4 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9FGP204 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Frequency Timing Generator for Peripherals |
| 9FGP204BKLF | 功能描述:時鐘合成器/抖動清除器 CK-MNG SERVER PERIPH ERAL CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9FGP204BKLFT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 CK-MNG SERVER PERIPH ERAL CLOCK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9FGP205 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Frequency Timing Generator for Peripherals |
| 9FGP205AKLF | 功能描述:時鐘合成器/抖動清除器 CK-MNG+ w/Wake-On- Lan RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。