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參數(shù)資料
| 型號： | 9FGP202AKLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 33.33 MHz, OTHER CLOCK GENERATOR, PQCC40 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MLF-40 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大小： | 137K |
| 代理商： | 9FGP202AKLFT |
13
Integrated
Circuit
Systems, Inc.
ICS9FGP202A
1339C—09/14/09
SMBus Table: CPU Frequency Select and Spread Spectrum Control Register
Byte 0
Name
Control Function
Type0
1
PWD
Bit 7
Reserved
RW
0
Bit 6
Reserved
Rev 0.20
0
Bit 5
Reserved
RW
0
Bit 4
DOT96 SS_EN
DOT96 Spread Spectrum Enable
RW
Disable
Enable
0
Bit 3
CPU SS_EN
CPU Spread Spectrum Enable
RW
0
Bit 2
CPU FS2
CPU Freq Select Bit 2
RW
0
Bit 1
CPU FS1
CPU Freq Select Bit 1
RW
1
Bit 0
CPU FS0
CPU Freq Select Bit 0
RW
0
SMBus Table: RMII Output Control Register
Byte 1
Name
Control Function
Type0
1
PWD
Bit 7
RMII_7 Enable
RMII_7 Output Control
RW
Disable
Enable
1
Bit 6
RMII_6 Enable
RMII_6 Output Control
RW
Disable
Enable
1
Bit 5
RMII_5 Enable
RMII_5 Output Control
RW
Disable
Enable
1
Bit 4
RMII_4 Enable
RMII_4 Output Control
RW
Disable
Enable
1
Bit 3
RMII_3 Enable
RMII_3 Output Control
RW
Disable
Enable
1
Bit 2
RMII_2 Enable
RMII_2 Output Control
RW
Disable
Enable
1
Bit 1
RMII_1 Enable
RMII_1 Output Control
RW
Disable
Enable
1
Bit 0
RMII_0 Enable
RMII_0 Output Control
RW
Disable
Enable
1
SMBus Table: DOT, CPU, 32.768KHz, 25MHz and 33.33MHz Outputs Control Register
Byte 2
Name
Control Function
Type0
1
PWD
Bit 7
CPUCLK PD Drive Mode
Driven in PD
RW
Driven
Hi-Z
0
Bit 6
DOT96SS PD Drive Mode
Driven in PD
RW
Driven
Hi-Z
0
Bit 5
33.33MHz Enable
33.33MHz Output Control
RW
Disable
Enable
1
Bit 4
25MHz_1 Enable
25MHz_1 Output Control
RW
Disable
Enable
1
Bit 3
25MHz_0 Enable
25MHz_0 Output Control
RW
Disable
Enable
1
Bit 2
32.768kHz Enable
32.768KHz Output Control
RW
Disable
Enable
1
Bit 1
CPUCLK Enable
CPUCLK Output Control
RW
Disable
Enable
1
Bit 0
DOT96SS Enable
DOT96SS Output Control
RW
Disable
Enable
1
SMBus Table: DOT96 Frequency Select and Spread Spectrum Control Register
Byte 3
Name
Control Function
Type0
1
PWD
Bit 7
Reserved
RW
0
Bit 6
Reserved
RW
0
Bit 5
Reserved
RW
0
Bit 4
Reserved
RW
0
Bit 3
DOT96SS FS3
DOT96 Freq Select Bit 3
RW
0
Bit 2
DOT96SS FS2
DOT96 Freq Select Bit 2
RW
0
Bit 1
DOT96SS FS1
DOT96 Freq Select Bit 1
RW
0
Bit 0
DOT96SS FS0
DOT96 Freq Select Bit 0
RW
0
SMBus Table: RMII Strength Control Register
Byte 4
Name
Control Function
Type0
1
PWD
Bit 7
RMII_7 Str
RMII_7 Strength Control
RW
1-Load (1X)
2-Loads (2X)
0
Bit 6
RMII_6 Str
RMII_6 Strength Control
RW
1-Load (1X)
2-Loads (2X)
0
Bit 5
RMII_5 Str
RMII_5 Strength Control
RW
1-Load (1X)
2-Loads (2X)
0
Bit 4
RMII_4 Str
RMII_4 Strength Control
RW
1-Load (1X)
2-Loads (2X)
0
Bit 3
RMII_3 Str
RMII_3 Strength Control
RW
1-Load (1X)
2-Loads (2X)
0
Bit 2
RMII_2 Str
RMII_2 Strength Control
RW
1-Load (1X)
2-Loads (2X)
0
Bit 1
RMII_1 Str
RMII_1 Strength Control
RW
1-Load (1X)
2-Loads (2X)
0
Bit 0
RMII_0 Str
RMII_0 Strength Control
RW
1-Load (1X)
2-Loads (2X)
0
24
Pin #
Reserved
Pin #
37
36
33
Reserved
See Table 1:
CPU Frequency Selection Table
Reserved
See Table 2:
DOT Frequency Selection Table
-
32
29
28
25
-
13
-
6
5
16
-
Reserved
-
Reserved
-
24
36
28
29
32
33
-
Pin #
25
-
37
7,8
-
3,4
22
17
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| 9FGP204 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Frequency Timing Generator for Peripherals |
| 9FGP204BKLF | 功能描述:時鐘合成器/抖動清除器 CK-MNG SERVER PERIPH ERAL CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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