參數(shù)資料
型號(hào): 9FGP202AKLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 33.33 MHz, OTHER CLOCK GENERATOR, PQCC40
封裝: ROHS COMPLIANT, PLASTIC, MLF-40
文件頁(yè)數(shù): 6/18頁(yè)
文件大小: 137K
代理商: 9FGP202AKLFT
14
Integrated
Circuit
Systems, Inc.
ICS9FGP202A
1339C—09/14/09
SMBus Table: 32.768KHz, 25Mhz and 33.33MHz Strength Control Register
Byte 5
Name
Control Function
Type0
1
PWD
Bit 7
Reserved
RW
Reserved
0
Bit 6
Reserved
RW
Reserved
0
Bit 5
33.33MHz Str
33.33MHz Strength Control
RW
1-Load (1X)
2-Loads (2X)
1
Bit 4
25MHz_1 Str
25MHz_1 Strength Control
RW
1-Load (1X)
2-Loads (2X)
1
Bit 3
25MHz_0 Str
25MHz_1 Strength Control
RW
1-Load (1X)
2-Loads (2X)
1
Bit 2
32.768kHz Str
32.768kHz Strength Control
RW
1-Load (1X)
2-Loads (2X)
1
Bit 1
Reserved
RW
Reserved
0
Bit 0
Reserved
RW
Reserved
0
SMBus Table: Vendor & Revision ID Register
Byte 6
Name
Control Function
Type0
1
PWD
Bit 7
RID3
R
-
X
Bit 6
RID2
R
-
X
Bit 5
RID1
R
-
X
Bit 4
RID0
R
-
X
Bit 3
VID3
R
-
0
Bit 2
VID2
R
-
0
Bit 1
VID1
R
-
0
Bit 0
VID0
R
-
1
SMBus Table: Device ID
Byte 7
Name
Control Function
Type0
1
PWD
Bit 7
Device ID 7 (MSB)
RW
0
Bit 6
Device ID 6
RW
0
Bit 5
Device ID 5
RW
1
Bit 4
Device ID 4
RW
0
Bit 3
Device ID 3
RW
0
Bit 2
Device ID 2
RW
0
Bit 1
Device ID 1
RW
1
Bit 0
Device ID 0 (LSB)
RW
0
SMBus Table: Byte Count Register
Byte 8
Name
Control Function
Type0
1
PWD
Bit 7
BC7
RW
-
0
Bit 6
BC6
RW
-
0
Bit 5
BC5
RW
-
0
Bit 4
BC4
RW
-
0
Bit 3
BC3
RW
-
1
Bit 2
BC2
RW
-
0
Bit 1
BC1
RW
-
0
Bit 0
BC0
RW
-
1
SMBus Table: Reserved
Byte 9
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: PLLs M/N Programming Enable Register
Byte 10
Name
Control Function
Type0
1
PWD
Bit 7
M/N_EN
PLLs M/N Programming Enable
RW
Disable
Enable
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Pin #
-
22
17
16
13
Pin #
-
Device ID
Reserved
-
Writing to this register configures
how many bytes will be read back.
-
Pin #
-
Reserved
REVISION ID
-
VENDOR ID
-
Pin #
-
Reserved
Pin #
Reserved
Pin #
-
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