參數(shù)資料
型號(hào): 9FGP202AKLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 33.33 MHz, OTHER CLOCK GENERATOR, PQCC40
封裝: ROHS COMPLIANT, PLASTIC, MLF-40
文件頁(yè)數(shù): 4/18頁(yè)
文件大?。?/td> 137K
代理商: 9FGP202AKLFT
12
Integrated
Circuit
Systems, Inc.
ICS9FGP202A
1339C—09/14/09
General SMBus serial interface information for the ICS9FGP202A
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address *D0
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address *D0
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address *D1
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
P
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
stoP bit
X
By
te
Index Block Write Operation
Slave Address *D0(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
PstoP bit
ICS (Slave/Receiver)
Controller (Host)
X
B
y
te
ACK
Data Byte Count = X
ACK
Slave Address *D1(H)
Index Block Read Operation
Slave Address *D0(H)
Beginning Byte = N
ACK
* By default, SMBADR = 0,
therefore, SMBus WRITE/READ address is D0/D1.
Please see SMBus Address Selection table on page 1.
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