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參數(shù)資料
| 型號(hào)： | 9S12D32DGV1 |
| 英文描述： | 9S12DGDJ64DGV1 Device Guide. also covers 9S12D64. 9S12A64. 9S12D32. and 9S12A32 devices |
| 中文描述： | 9S12DGDJ64DGV1設(shè)備指南。也包括9S12D64。 9S12A64。 9S12D32。和9S12A32設(shè)備 |
| 文件頁(yè)數(shù)： | 2/126頁(yè) |
| 文件大?。?/td> | 1809K |
| 代理商： | 9S12D32DGV1 |
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Revision History
Version
Number
Revision
Date
16 NOV
2001
Effective
Date
19 NOV
2001
Author
Description of Changes
V01.00
Initial version based on MC9SDP256-2.09 Version.
V01.01
18 FEB
2002
18 FEB
2002
In table 7 I/O Characteristics" of the electrical characteristics
replaced tPULSE with tpign and tpval in lines "Port ... Interrupt Input
Pulse filtered" and "Port ... Interrupt Input Pulse passed"
respectively.
Table "Oscillator Characteristics": removed "Oscillator start-up time
from POR or STOP" row
Table "5V I/O Characteristics": Updated
Partial Drive IOH = +–2mA and Full Drive IOH = –10mA
Table "ATD Operating Characteristics": Distinguish I
REF
for 1 and 2
ATD blocks on
Table "ATD Electrical Characteristics": Update C
INS
to 22 pF
Table "Operating Conditions": Changed V
DD
and V
DDPLL
to 2.35 V
(min)
Removed Document number except from Cover Sheet
Updated Table "Document References"
Table "5V I/O Characteristics" : Corrected Input Capacitance to 6pF
Section: "Device Pinout" (112-pin and 80-pin): added in diagrams
RXCAN0 to PJ6 and TXCAN0 to PJ7
Table "PLL Characteristics": Updated parameters K
1
and f
1
Figure "Basic PLL functional diagram": Inserted XFC pin in diagram
Enhanced section "XFC Component Selection"
Added to Sections ATD, ECT and PWM: freeze mode = active BDM
mode
Added 1L86D to Table "Assigned Part ID numbers"
Corrected MEMSIZ1 value in Table "Memory size registers"
Subsection "Device Memory Map: Removed Flash mapping from
$0000 to $3FFF.
Table "Signal Properties": Added column "Internal Pull Resistor".
Preface Table "Document References": Changed to full naming for
each block.
Table "Interrupt Vector Locations", Column "Local Enable":
Corrected several register and bit names.
Figure "Recommended PCB Layout for 80QFP: Corrected
VREGEN pin position
Thermal values for junction to board and package
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
Modified mode of Operations chapter
Section "Printed Circuit Board Layout Proposals": added Pierce
Oscillator examples for 112LQFP and 80QFP
V01.02
6 MAR
2002
6 MAR
2002
V01.03
4 June
2002
4 June
2002
V01.04
4 July
2002
4 July
2002
V01.05
30 July
2002
30 July
2002
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PDF描述 |
|---|---|
| 9S12DJ64DGV1 | 9S12DJ64DG Device Guide. also covers 9S12D64. 9S12A64. 9S12D32 and 9S12A32 devices |
| 9S12DJ64-ZIP_PART2 | MC9S12DJ64 Users Guides. zip format. part 2 |
| 9S12DP256BDGV2 | 9S12Dx256B Device Guide. also covers C derivatives and 9S12Ax256 devices |
| 9S12DP512DGV1 | 9S12Dx512 Device Guide |
| 9S12DT128BDGV1 | 9S12DT128B Device Guide |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9S12DJ64DGV1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12DJ64DG Device Guide. also covers 9S12D64. 9S12A64. 9S12D32 and 9S12A32 devices |
| 9S12DP256BDGV1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Automotive applications |
| 9S12DP256BDGV2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12Dx256B Device Guide. also covers C derivatives and 9S12Ax256 devices |
| 9S12DP512DGV1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12Dx512 Device Guide |
| 9S12DT128BDGV1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12DT128B Device Guide |
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