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Central Processing Unit (CPU)
MC9S12T64Revision 1.1.1
38
Central Processing Unit (CPU)
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MOTOROLA
ASL
opr16a
Same as LSL
ASL
oprx0_xysp
ASL
oprx9
,
xysppc
ASL
oprx16
,
xysppc
ASL[D,
xysppc
]
ASL[
oprx16
,
xysppc
]
ASLASame as LSLA
ASLBSame as LSLB
ASLDSame as LSLD
Arithmetic shift left M
ArithmeticshiftleftA
ArithmeticshiftleftB
ArithmeticshiftleftD
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
INH
78 hh ll
68 xb
68 xb ff
68 xb ee ff
68 xb
68 xb ee ff
48
58
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
59
O
ASR
opr16a
ASR
oprx0_xysppc
ASR
oprx9
,
xysppc
ASR
oprx16
,
xysppc
ASR[D,
xysppc
]
ASR[
oprx16
,
xysppc
]
ASRA
ASRB
ArithmeticshiftrightM
ArithmeticshiftrightA
ArithmeticshiftrightB
BranchifCclear; if C=0, then
(PC)+2+rel
PC
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
77 hh ll
67 xb
67 xb ff
67 xb ee ff
67 xb
67 xb ee ff
47
57
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
BCC
rel8
Same as BHS
REL
24 rr
PPP
(branch)
P
(no branch)
BCLR
opr8a
,
msk8
BCLR
opr16a
,
msk8
BCLR
oprx0_xysppc
,
msk8
BCLR
oprx9
,
xysppc
,
msk8
BCLR
oprx16
,
xysppc
,
msk8
BCS
rel8
Same as BLO
Clearbit(s)inM;(M)
mask byte
M
DIR
EXT
IDX
IDX1
IDX2
REL
4D dd mm
1D hh ll mm
0D xb mm
0D xb ff mm
0D xb ee ff mm
rPwO
rPwP
rPwO
rPwP
frPwPO
PPP
(branch)
P
(no branch)
PPP
(branch)
P
(no branch)
PPP
(branch)
P
(no branch)
BranchifCset;if C=1, then
(PC)+2+rel
PC
Branchifequal; if Z=1, then
(PC)+2+rel
PC
Branchif
≥
0, signed;ifN
⊕
V=0,then
(PC)+2+rel
PC
Enterbackgrounddebugmode
25 rr
BEQ
rel8
REL
27 rr
BGE
rel8
REL
2C rr
BGND
INH
00
VfPPP
BGT
rel8
Branch if
>
0, signed; ifZ | (N
⊕
V)=0,
then (PC)+2+rel
PC
Branch if higher, unsigned; if
C | Z=0,then (PC)+2+rel
PC
Branchifhigherorsame,unsigned;if
C=0,then(PC)+2+rel
PC
BittestA;(A)
(M)
or (A)
imm
REL
2E rr
PPP
(branch)
P
(no branch)
PPP
(branch)
P
(no branch)
PPP
(branch)
P
(no branch)
BHI
rel8
REL
22 rr
BHS
rel8
Same as BCC
REL
24 rr
BITA#
opr8i
BITA
opr8a
BITA
opr16a
BITA
oprx0_xysppc
BITA
oprx9
,
xysppc
BITA
oprx16
,
xysppc
BITA[D,
xysppc
]
BITA[
oprx16
,
xysppc
]
BITB#
opr8i
BITB
opr8a
BITB
opr16a
BITB
oprx0_xysppc
BITB
oprx9
,
xysppc
BITB
oprx16
,
xysppc
BITB[D,
xysppc
]
BITB[
oprx16
,
xysppc
]
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
85 ii
95 dd
B5 hh ll
A5 xb
A5 xb ff
A5 xb ee ff
A5 xb
A5 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
BittestB;(B)
(M)
or (B)
imm
C5 ii
D5 dd
F5 hh ll
E5 xb
E5 xb ff
E5 xb ee ff
E5 xb
E5 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
Table 4 Instruction Set Summary (Continued)
Source Form
Operation
Address
Mode
Machine
Coding (Hex)
Access Detail
S X H I N Z V C
C
0
b7
b0
– – – –
A
B
C
0
b7
b0
b7
b0
– – – –
C
b7
b0
– – – –
– – – – – – – –
– – – –
0 –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – –
0 –
– – – –
0 –
F
Freescale Semiconductor, Inc.
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.