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Central Processing Unit (CPU)
MC9S12T64Revision 1.1.1
48
Central Processing Unit (CPU)
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MOTOROLA
SBCA#
opr8i
SBCA
opr8a
SBCA
opr16a
SBCA
oprx0_xysppc
SBCA
oprx9
,
xysppc
SBCA
oprx16
,
xysppc
SBCA[D,
xysppc
]
SBCA[
oprx16
,
xysppc
]
SBCB#
opr8i
SBCB
opr8a
SBCB
opr16a
SBCB
oprx0_xysppc
SBCB
oprx9
,
xysppc
SBCB
oprx16
,
xysppc
SBCB[D,
xysppc
]
SBCB[
oprx16
,
xysppc
]
SECSame as ORCC #$01
Subtractwithcarryfrom A
(A)–(M)–C
A
or (A)–imm–C
A
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
IMM
82 ii
92 dd
B2 hh ll
A2 xb
A2 xb ff
A2 xb ee ff
A2 xb
A2 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
Subtractwithcarryfrom B
(B)–(M)–C
B
or (B)–imm–C
B
C2 ii
D2 dd
F2 hh ll
E2 xb
E2 xb ff
E2 xb ee ff
E2 xb
E2 xb ee ff
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
Set C bit
14 01
P
SEISame as ORCC #$10
Set I bit
IMM
14 10
P
SEVSame asORCC#$02
Set V bit
IMM
14 02
P
SEX
abc
,
dxysp
Same as TFR r1, r2
Sign extend; 8-bit r1 to 16-bit r2
$00:(r1)
r2 if bit 7 of r1 is 0
$FF:(r1)
r2 if bit 7 of r1 is 1
StoreaccumulatorA
(A)
M
INH
B7 eb
P
STAA
opr8a
STAA
opr16a
STAA
oprx0_xysppc
STAA
oprx9
,
xysppc
STAA
oprx16
,
xysppc
STAA[D,
xysppc
]
STAA[
oprx16
,
xysppc
]
STAB
opr8a
STAB
opr16a
STAB
oprx0_xysppc
STAB
oprx9
,
xysppc
STAB
oprx16
,
xysppc
STAB[D,
xysppc
]
STAB[
oprx16
,
xysppc
]
STD
opr8a
STD
opr16a
STD
oprx0_xysppc
STD
oprx9
,
xysppc
STD
oprx16
,
xysppc
STD[D,
xysppc
]
STD[
oprx16
,
xysppc
]
STOP
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
5A dd
7A hh ll
6A xb
6A xb ff
6A xb ee ff
6A xb
6A xb ee ff
Pw
PwO
Pw
PwO
PwP
PIfw
PIPw
StoreaccumulatorB
(B)
M
5B dd
7B hh ll
6B xb
6B xb ff
6B xb ee ff
6B xb
6B xb ee ff
Pw
PwO
Pw
PwO
PwP
PIfw
PIPw
StoreD
(A:B)
M:M+1
5C dd
7C hh ll
6C xb
6C xb ff
6C xb ee ff
6C xb
6C xb ee ff
PW
PWO
PW
PWO
PWP
PIfW
PIPW
OOSSSSsf
(enter
stop mode)
fVfPPP
(exit stop
mode)
ff
(continue stop
mode)
OO
(if stop mode
disabled by S=1)
Stop processing; (SP)–2
SP
RTN
H
:RTN
L
M
SP
:M
SP+1
(SP)–2
SP; (Y
H
:Y
L
)
M
SP
:M
SP+1
(SP)–2
SP; (X
H
:X
L
)
M
SP
:M
SP+1
(SP)–2
SP; (B:A)
M
SP
:M
SP+1
(SP)–1
SP; (CCR)
M
SP
Stop all clocks
18 3E
Table 4 Instruction Set Summary (Continued)
Source Form
Operation
Address
Mode
Machine
Coding (Hex)
Access Detail
S X H I N Z V C
– – – –
– – – –
– – – – – – – 1
– – – 1 – – – –
– – – – – – 1 –
– – – – – – – –
– – – –
0 –
– – – –
0 –
– – – –
0 –
– – – – – – – –
F
Freescale Semiconductor, Inc.
n
.