Table 2-19 A1415A, A" />
參數(shù)資料
型號(hào): A14100A-1BG313C
廠商: Microsemi SoC
文件頁(yè)數(shù): 25/90頁(yè)
文件大?。?/td> 0K
描述: IC FPGA 10K GATES 313-BGA
標(biāo)準(zhǔn)包裝: 24
系列: ACT™ 3
LAB/CLB數(shù): 1377
輸入/輸出數(shù): 228
門數(shù): 10000
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 313-BBGA
供應(yīng)商設(shè)備封裝: 313-PBGA(35x35)
Accelerator Series FPGAs – ACT 3 Family
R e visio n 3
2 - 23
A1415A, A14V15A Timing Characteristics (continued)
Table 2-19 A1415A, A14V15A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
I/O Module Input Propagation Delays
–3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed2 Units
Parameter/Description
Min. Max. Min. Max. Min. Max. Min. Max.
Min.
Max.
tINY
Input Data Pad to Y
2.8
3.2
3.6
4.2
5.5
ns
tICKY
Input Reg IOCLK Pad to Y
4.7
5.3
6.0
7.0
9.2
ns
tOCKY
Output Reg IOCLK Pad to Y
4.7
5.3
6.0
7.0
9.2
ns
tICLRY Input Asynchronous Clear to Y
4.7
5.3
6.0
7.0
9.2
ns
tOCLRY Output Asynchronous Clear to Y
4.7
5.3
6.0
7.0
9.2
ns
Predicted Input Routing Delays2
tRD1
FO = 1 Routing Delay
0.9
1.0
1.1
1.3
1.7
ns
tRD2
FO = 2 Routing Delay
1.2
1.4
1.6
1.8
2.4
ns
tRD3
FO = 3 Routing Delay
1.4
1.6
1.8
2.1
2.8
ns
tRD4
FO = 4 Routing Delay
1.7
1.9
2.2
2.5
3.3
ns
tRD8
FO = 8 Routing Delay
2.8
3.2
3.6
4.2
5.5
ns
I/O Module Sequential Timing (wrt IOCLK pad)
tINH
Input F-F Data Hold
0.0
ns
tINSU
Input F-F Data Setup
2.0
2.3
2.5
3.0
ns
tIDEH
Input Data Enable Hold
0.0
ns
tIDESU Input Data Enable Setup
5.8
6.5
7.5
8.6
ns
tOUTH
Output F-F Data hold
0.7
0.8
0.9
1.0
ns
tOUTSU Output F-F Data Setup
0.7
0.8
0.9
1.0
ns
tODEH Output Data Enable Hold
0.3
0.4
0.5
ns
fODESU Output Data Enable Setup
1.3
1.5
1.7
2.0
ns
Notes:
1. The –2 and –3 speed grades have been discontinued. Please refer to the Product Discontinuation Notices (PDNs) listed
below:
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to
shipment.
相關(guān)PDF資料
PDF描述
93AA46AT-I/MNY IC EEPROM SER 1K 1.8V 8TDFN
93LC46BT-I/MNY IC EEPROM SER 1K 2.5V 8TDFN
93LC46AT-I/MNY IC EEPROM SER 1K 2.5V 8TDFN
93C46BT-I/MNY IC EEPROM SER 1K 4.5V 8TDFN
93C46AT-I/MNY IC EEPROM SER 1K 4.5V 8TDFN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A14100A-1BG313I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
A14100A-1CQ256B 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 10K GATES 1377 CELLS 125MHZ 0.8UM 5V 256CQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 10K GATES 256-CQFP MIL
A14100A-1CQ256BX3 制造商:Microsemi Corporation 功能描述:FPGA,ACT3 FAMILY,OTP DEVICE,5V SINGLE LOT DATE CODE - Trays
A14100A-1CQ256C 功能描述:IC FPGA 10K GATES 256-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:ACT™ 3 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP,帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP(75x75)
A14100A-1CQ256E 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs