參數(shù)資料
型號(hào)： A14100A-1BG313C
廠(chǎng)商： Microsemi SoC
文件頁(yè)數(shù)： 8/90頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 10K GATES 313-BGA
標(biāo)準(zhǔn)包裝： 24
系列： ACT™ 3
LAB/CLB數(shù)： 1377
輸入/輸出數(shù)： 228
門(mén)數(shù)： 10000
電源電壓： 4.5 V ~ 5.5 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 313-BBGA
供應(yīng)商設(shè)備封裝： 313-PBGA（35x35）
Detailed Specifications
2- 8
R e v ision 3
Module Output Connections
Module outputs have dedicated output segments. Output segments extend vertically two channels above
and two channels below, except at the top or bottom of the array. Output segments twist, as shown in
Figure 10, so that only four vertical tracks are required.
LVT Connections
Outputs may also connect to nondedicated segments called Long Vertical Tracks (LVTs). Each module
pair in the array shares four LVTs that span the length of the column. Any module in the column pair can
connect to one of the LVTs in the column using an FF connection. The FF connection uses antifuses
connected directly to the driver stage of the module output, bypassing the isolation transistor. FF
antifuses are programmed at a higher current level than HF, VF, or XF antifuses to produce a lower
resistance value.
Antifuse Connections
In general every intersection of a vertical segment and a horizontal segment contains an unprogrammed
antifuse (XF-type). One exception is in the case of the clock networks.
Clock Connections
To minimize loading on the clock networks, a subset of inputs has antifuses on the clock tracks. Only a
few of the C-module and S-module inputs can be connected to the clock networks. To further reduce
loading on the clock network, only a subset of the horizontal routing tracks can connect to the clock
inputs of the S-module.
Programming and Test Circuits
The array of logic and I/O modules is surrounded by test and programming circuits controlled by the
temporary special I/O pins MODE, SDI, and DCLK. The function of these pins is similar to all ACT family
devices. The ACT 3 family also includes support for two Actionprobe circuits, allowing complete
observability of any logic or I/O module in the array using the temporary special I/O pins, PRA and PRB.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A14100A-1BG313I 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Field Programmable Gate Array (FPGA)
A14100A-1CQ256B 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 10K GATES 1377 CELLS 125MHZ 0.8UM 5V 256CQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 10K GATES 256-CQFP MIL
A14100A-1CQ256BX3 制造商:Microsemi Corporation 功能描述:FPGA,ACT3 FAMILY,OTP DEVICE,5V SINGLE LOT DATE CODE - Trays
A14100A-1CQ256C 功能描述:IC FPGA 10K GATES 256-CQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ACT™ 3 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門(mén)數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類(lèi)型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A14100A-1CQ256E 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:HiRel FPGAs
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