Table 2-24 A1425A, A14V25A Worst-Case" />
參數(shù)資料
型號： A1460A-1PG207C
廠商： Microsemi SoC
文件頁數(shù)： 30/90頁
文件大小： 0K
描述： IC FPGA 6K GATES 207-CPGA
標(biāo)準(zhǔn)包裝： 10
系列： ACT™ 3
LAB/CLB數(shù)： 848
輸入/輸出數(shù)： 168
門數(shù)： 6000
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 通孔
工作溫度： 0°C ~ 70°C
封裝/外殼： 207-BCPGA
供應(yīng)商設(shè)備封裝： 207-CPGA（44.96x44.96）
Detailed Specifications
2- 28
R e visio n 3
A1425A, A14V25A Timing Characteristics (continued)
Table 2-24 A1425A, A14V25A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
I/O Module – TTL Output Timing1
–3 Speed2 –2 Speed2 –1 Speed Std. Speed 3.3 V Speed1 Units
Parameter/Description
Min. Max. Min. Max. Min. Max. Min. Max.
Min.
Max.
tDHS
Data to Pad, High Slew
5.0
5.6
6.4
7.5
9.8
ns
tDLS
Data to Pad, Low Slew
8.0
9.0
10.2
12.0
15.6
ns
tENZHS Enable to Pad, Z to H/L, High Slew
4.0
4.5
5.1
6.0
7.8
ns
tENZLS Enable to Pad, Z to H/L, Low Slew
7.4
8.3
9.4
11.0
14.3
ns
tENHSZ Enable to Pad, H/L to Z, High Slew
6.5
7.5
8.5
10.0
13.0
ns
tENLSZ Enable to Pad, H/L to Z, Low Slew
6.5
7.5
8.5
10.0
13.0
ns
tCKHS
IOCLK Pad to Pad H/L, High Slew
7.5
9.0
10.0
13.0
ns
tCKLS
IOCLK Pad to Pad H/L, Low Slew
11.3
13.5
15.0
19.5
ns
dTLHHS Delta Low to High, High Slew
0.02
0.03
0.04
ns/pF
dTLHLS Delta Low to High, Low Slew
0.05
0.06
0.07
0.09
ns/pF
dTHLHS Delta High to Low, High Slew
0.04
0.05
0.07
ns/pF
dTHLLS Delta High to Low, Low Slew
0.05
0.06
0.07
0.09
ns/pF
I/O Module – CMOS Output Timing1
tDHS
Data to Pad, High Slew
6.2
7.0
7.9
9.3
12.1
ns
tDLS
Data to Pad, Low Slew
11.7
13.1
14.9
17.5
22.8
ns
tENZHS Enable to Pad, Z to H/L, High Slew
5.2
5.9
6.6
7.8
10.1
ns
tENZLS Enable to Pad, Z to H/L, Low Slew
8.9
10.0
11.3
13.3
17.3
ns
tENHSZ Enable to Pad, H/L to Z, High Slew
6.7
7.5
8.5
10.0
13.0
ns
tENLSZ Enable to Pad, H/L to Z, Low Slew
6.7
7.5
9.0
10.0
13.0
ns
tCKHS
IOCLK Pad to Pad H/L, High Slew
8.9
10.7
11.8
15.3
ns
tCKLS
IOCLK Pad to Pad H/L, Low Slew
13.0
15.6
17.3
22.5
ns
dTLHHS Delta Low to High, High Slew
0.04
0.05
0.06
0.08
ns/pF
dTLHLS Delta Low to High, Low Slew
0.07
0.08
0.09
0.11
0.14
ns/pF
dTHLHS Delta High to Low, High Slew
0.03
0.04
0.05
ns/pF
dTHLLS Delta High to Low, Low Slew
0.04
0.05
0.07
ns/pF
Notes: *
1. Delays based on 35 pF loading.
2. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at
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參數(shù)描述
A1460A-1PG207M 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 Family 6K Gates 848 Cells 125MHz 0.8um Technology 5V 207-Pin CPGA 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 6K GATES 848 CELLS 125MHZ 0.8UM 5V 207CPGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 6K GATES 207-CPGA
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