參數(shù)資料
型號(hào)： A1460A-1PG207C
廠商： Microsemi SoC
文件頁(yè)數(shù)： 4/90頁(yè)
文件大小： 0K
描述： IC FPGA 6K GATES 207-CPGA
標(biāo)準(zhǔn)包裝： 10
系列： ACT™ 3
LAB/CLB數(shù)： 848
輸入/輸出數(shù)： 168
門(mén)數(shù)： 6000
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 通孔
工作溫度： 0°C ~ 70°C
封裝/外殼： 207-BCPGA
供應(yīng)商設(shè)備封裝： 207-CPGA（44.96x44.96）
Detailed Specifications
2- 4
R e v ision 3
The I/O module output Y is used to bring Pad signals into the array or to feed the output register back into
the array. This allows the output register to be used in high-speed state machine applications. Side I/O
modules have a dedicated output segment for Y extending into the routing channels above and below
(similar to logic modules). Top/Bottom I/O modules have no dedicated output segment. Signals coming
into the chip from the top or bottom are routed using F-fuses and LVTs (F-fuses and LVTs are explained
in detail in the routing section).
I/O Pad Drivers
All pad drivers are capable of being tristate. Each buffer connects to an associated I/O module with four
signals: OE (Output Enable), IE (Input Enable), DataOut, and DataIn. Certain special signals used only
during programming and test also connect to the pad drivers: OUTEN (global output enable), INEN
(global input enable), and SLEW (individual slew selection). See Figure 2-5.
Special I/Os
The special I/Os are of two types: temporary and permanent. Temporary special I/Os are used during
programming and testing. They function as normal I/Os when the MODE pin is inactive. Permanent
special I/Os are user programmed as either normal I/Os or special I/Os. Their function does not change
once the device has been programmed. The permanent special I/Os consist of the array clock input
buffers (CLKA and CLKB), the hard-wired array clock input buffer (HCLK), the hard-wired I/O clock input
buffer (IOCLK), and the hard-wired I/O register preset/clear input buffer (IOPCL). Their function is
determined by the I/O macros selected.
Clock Networks
The ACT 3 architecture contains four clock networks: two high-performance dedicated clock networks
and two general purpose routed networks. The high-performance networks function up to 200 MHz,
while the general purpose routed networks function up to 150 MHz.
Figure 2-5
Function Diagram for I/O Pad Driver
PAD
OE
SLEW
DATAOUT
DATAIN
IEN
INEN
OUTEN
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A1460A-1PG207M 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 Family 6K Gates 848 Cells 125MHz 0.8um Technology 5V 207-Pin CPGA 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 6K GATES 848 CELLS 125MHZ 0.8UM 5V 207CPGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 6K GATES 207-CPGA
A1460A-1PG256B 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs
A1460A-1PG256C 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs
A1460A-1PG256E 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs
A1460A-1PG256M 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs
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