2-50 Revision 13 3.3 V LVCMOS Wide Range Table 2-62 Minimum and Maximum DC Input and Out" />
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寤犲晢锛� Microsemi SoC
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绯诲垪锛� ProASIC3L
RAM 浣嶇附瑷�(j矛)锛� 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 235
闁€(m茅n)鏁�(sh霉)锛� 600000
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灏佽/澶栨锛� 484-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 484-FPBGA锛�23x23锛�
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ProASIC3L DC and Switching Characteristics
2-50
Revision 13
3.3 V LVCMOS Wide Range
Table 2-62 Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range
Applicable to Pro I/O Banks
3.3 V
LVCMOS
Wide
Range
Equivalent
Software
Default
Drive
Strength
Option1
VIL
VIH
VOL
VOH
IOL IOH IOSH IOSL
IIL
IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VA
A
Max.
mA2
Max.
mA2
A
100 A
2 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100
100
25
27
10
100 A
4 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100
100
25
27
10
100 A
6 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100
100
51
54
10
100 A
8 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100
100
51
54
10
100 A
12 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100
100
103
109
10
100 A
16 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100
100
132
127
10
100 A
24 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100
100
268
181
10
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 卤100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. Currents are measured at 85掳C junction temperature.
3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-B specification
4. Software default selection highlighted in gray.
Table 2-63 Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range
Applicable to Advanced I/O Banks
3.3 V
LVCMOS
Wide
Range
Equivalent
Software
Default
Drive
Strength
Option1
VIL
VIH
VOL
VOH
IOL IOH IOSH IOSL
IIL
IIH
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VA
A
Max.
mA2
Max.
mA2
A
100 A
2 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100
100
25
27
10
100 A
4 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100
100
25
27
10
100 A
6 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100
100
51
54
10
100 A
8 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100
100
51
54
10
100 A
12 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100
100
51
54
10
100 A
16 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100
100
103
109
10
100 A
24 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100
100
132
127
10
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 卤100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. Currents are measured at 85掳C junction temperature.
3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8-B specification
4. Software default selection highlighted in gray.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
AMC26DRXI-S734 CONN EDGECARD 52POS DIP .100 SLD
GBB95DHBT CONN EDGECARD 190PS R/A .050 SLD
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AGL400V2-FGG256I IC FPGA 1KB FLASH 400K 256FBGA
M1A3P1000L-FG144I IC FPGA M1 1KB FLASH 1M 144FBGA
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A3P600L-1FGG144 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 600K 144-FBGA RoHS:鏄� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:ProASIC3L 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€(m茅n)鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
A3P600L-1FGG144I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 600K 144-FBGA RoHS:鏄� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:ProASIC3L 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€(m茅n)鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
A3P600L-1FGG256 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 600K 256-FBGA RoHS:鏄� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:ProASIC3L 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€(m茅n)鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
A3P600L-1FGG256I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 600K 256-FBGA RoHS:鏄� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:ProASIC3L 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€(m茅n)鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A3P600L-1FGG484 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 600K 484-FBGA RoHS:鏄� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:ProASIC3L 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€(m茅n)鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�