參數(shù)資料
型號(hào): A40MX04-PLG68A
元件分類(lèi): FPGA
英文描述: FPGA, 6000 GATES, PQCC68
封裝: PLASTIC, LCC-68
文件頁(yè)數(shù): 39/76頁(yè)
文件大?。?/td> 429K
代理商: A40MX04-PLG68A
MX Automotive Family FPGAs
1- 3 8
v2 .0
Table 1-10 A42MX36 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125°C
‘Std’ Speed
Parameter
Description
Min.
Max.
Units
Logic Module Combinatorial Functions1
tPD
Internal Array Module Delay
2.4
ns
tPDD
Internal Decode Module Delay
2.8
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
1.6
ns
tRD2
FO=2 Routing Delay
2.2
ns
tRD3
FO=3 Routing Delay
2.8
ns
tRD4
FO=4 Routing Delay
3.4
ns
tRD5
FO=8 Routing Delay
5.8
ns
tRDD
Decode-to-Output Routing Delay
0.6
ns
Logic Module Sequential Timing3, 4
tCO
Flip-Flop Clock-to-Output
2.2
ns
tGO
Latch Gate-to-Output
2.2
ns
tSU
Flip-Flop (Latch) Set-Up Time
0.6
ns
tH
Flip-Flop (Latch) Hold Time
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
2.7
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
1.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock
Active Pulse Width
5.8
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
7.5
ns
Synchronous SRAM Operations
tRC
Read Cycle Time
11.8
ns
tWC
Write Cycle Time
11.8
ns
tRCKHL
Clock HIGH/LOW Time
5.9
ns
tRCO
Data Valid After Clock HIGH/LOW
5.9
ns
tADSU
Address/Data Set-Up Time
2.8
ns
tADH
Address/Data Hold Time
0.0
ns
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
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