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參數(shù)資料
| 型號： | A40MX04-PLG68A |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 6000 GATES, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 5/76頁 |
| 文件大?。?/td> | 429K |
| 代理商： | A40MX04-PLG68A |
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MX Automotive Family FPGAs
v2.0
1-7
When a device is operating in BST mode, four I/O pins are
used for the TDI, TDO, TMS, and TCK signals. An active
reset (TRST) pin is not supported; however, the A42MX24
and A42MX36 devices contain power-on circuitry that
resets the boundary scan circuitry upon power-up.
Table 1-1 summarizes the functions of the IEEE 1149.1
BST signals.
JTAG
A42MX24 and A42MX36 automotive-grade MX devices
offer superior diagnostic and testing capabilities by
providing JTAG and probing capabilities. These functions
are
controlled
through
the
special
JTAG
pins
in
conjunction with the program fuse.
JTAG fuse programmed:
TCK must be terminated—logical high or low doesn’t
matter (to avoid floating input)
TDI, TMS may float or at logical high (internal pull-up
is present)
TDO may float or connect to TDI of another device
(it’s an output)
JTAG fuse not programmed:
TCK, TDI, TDO, TMS are user I/O. If not used, they will
be configured as tri-stated output.
BST Instructions
Boundary
scan
testing
within
the
A42MX24
and
A42MX36 devices is controlled by a Test Access Port (TAP)
state machine. The TAP controller drives the three-bit
instruction register, a bypass register, and the boundary
scan data registers within the device. The TAP controller
uses the TMS signal to control the testing of the device.
The BST mode is determined by the bitstream entered on
the TMS pin. Table 1-2 describes the test instructions
supported by the A42MX24 and A42MX36 devices.
Reset
The TMS pin is equipped with an internal pull-up resistor.
This allows the TAP controller to remain in or return to
the Test-Logic-Reset state when there is no input or
when a logical 1 is on the TMS pin. To reset the
controller, TMS must be HIGH for at least five TCK cycles.
Development Tool Support
The automotive-grade MX family of FPGAs is fully
supported by both Actel's Libero Integrated Design
Environment and Designer FPGA Development software.
Actel Libero IDE is a design management environment
that streamlines the design flow. Libero IDE provides an
integrated design manager that seamlessly integrates
design tools while guiding the user through the design
flow, managing all design and log files, and passing
necessary design data among tools. Additionally, Libero
IDE allows users to integrate both schematic and HDL
synthesis into a single flow and verify the entire design
in a single environment (Figure 1-11 on page 1-8). Libero
IDE includes Synplify for Actel from Synplicity,
ViewDraw for Actel from Mentor Graphics, ModelSim
HDL Simulator from Model Technology, WaveFormer
Lite from SynaptiCAD, and Designer software from
Actel.
Actel's Designer software provides a comprehensive suite
of backend development tools for FPGA development.
The Designer software includes timing-driven place-and-
route, and a world-class integrated static timing analyzer
and constraints editor. With the Designer software, a
user can lock his/her design pins before layout while
minimally impacting the results of place-and-route.
Additionally, the back-annotation flow is compatible
Table 1-1 IEEE 1149.1 BST Signals
Signal Name
Function
TDI
Test Data In
Serial data input for BST instructions
and data. Data is shifted in on the
rising edge of TCK.
TDO
Test Data Out
Serial
data
output
for
BST
instructions and test data.
TMS
Test Mode Select Serial data input for BST mode.
Data is shifted in on the rising edge
of TCK.
TCK
Test Clock
Clock signal to shift the BST data
into the device.
Table 1-2 BST Instructions
Test Mode
Code
Description
EXTEST
000
Allows the external circuitry and board-
level interconnections to be tested by
forcing a test pattern at the output pins
and capturing test results at the input
pins.
SAMPLE/
PRELOAD
001
Allows a snapshot of the signals at the
device pins to be captured and examined
during device operation.
HIGH Z
101
Refer to the IEEE Standard 1149.1
specification.
CLAMP
110
Refer to the IEEE Standard 1149.1
specification.
BYPASS
111
Enables the bypass register between the
TDI and TDO pins. The test data passes
through the selected device to adjacent
devices in the test chain.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A40MX04-PLG68I | 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設備封裝:256-FPBGA（17x17） |
| A40MX04-PLG68M | 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 68PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 57 I/O 68PLCC 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC |
| A40MX04-PLG84 | 功能描述:IC FPGA 69I/O 84PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計:226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） |
| A40MX04-PLG84A | 功能描述:IC FPGA MX SGL CHIP 6K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設備封裝:256-FPBGA（17x17） |
| A40MX04-PLG84I | 功能描述:IC FPGA MX SGL CHIP 6K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應商設備封裝:256-FPBGA（17x17） |
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