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參數(shù)資料
| 型號： | A40MX04-PLG68A |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 6000 GATES, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 76/76頁 |
| 文件大?。?/td> | 429K |
| 代理商： | A40MX04-PLG68A |
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MX Automotive Family FPGAs
v2.0
1-3
D-modules, available in A42MX24 and A42MX36 devices,
contain wide-decode circuitry which provide a fast, wide-
input AND function similar to that found in CPLD
architectures (Figure 1-4). These modules are arranged
around the periphery of the device. The D-module allows
42MX devices to perform wide-decode functions at
speeds comparable to CPLDs and PALs. The output of the
D-module has a programmable inverter for active HIGH
or LOW assertion. The D-module output is hard-wired to
an output pin, but it can also be fed back into the array
to be incorporated into other logic.
Dual-Port SRAM Modules
The A42MX36 device contains dual-port SRAM modules
that
have
been
optimized
for
synchronous
or
asynchronous applications. The SRAM modules are
arranged in 256-bit blocks that can be configured as 32x8
or 64x4. SRAM modules can be cascaded together to
form memory spaces of user-definable width and depth.
A block diagram of the 42MX dual-port SRAM block is
shown in Figure 1-5.
The 42MX SRAM modules are true dual-port structures
containing independent read and write ports. Each
SRAM module contains six bits of read and write
addressing (RDAD[5:0] and WRAD[5:0], respectively) for
64x4-bit blocks. When configured in byte mode, the
highest order address bits (RDAD5 and WRAD5) are not
used. The read and write ports of the SRAM block
contain independent clocks (RCLK and WCLK) with
programmable polarities offering active HIGH or LOW
implementation. The SRAM block contains eight data
inputs (WD[7:0]), and eight outputs (RD[7:0]) which are
connected to segmented vertical routing tracks.
The 42MX dual-port SRAM blocks provide an optimal
solution for high-speed buffered applications requiring
fast FIFO and LIFO queues. Actel’s ACTgen Macro Builder
provides the capability to quickly design memory
functions, such as FIFOs, LIFOs, and RAM arrays. In
addition, unused SRAM blocks can be used to implement
registers for other logic within the design.
Figure 1-4 D-Module Implementation in 42MX Devices
7 Inputs
Hard-Wire to I/O
Feedback to Array
Programmable
Inverter
Figure 1-5 42MX Dual-Port SRAM Block
SRAM Module
32 x 8 or 64 x 4
(256 Bits)
Read
Port
Logic
Write
Port
Logic
RD[7:0]
Routing Tracks
[5:0]
RDAD[5:0]
REN
RCLK
Latches
WD[7:0]
WRAD[5:0]
Write
Logic
MODE
BLKEN
WEN
WCLK
[5:0]
Latches
Read
Logic
[7:0]
Latches
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX36-BG272A | FPGA, 54000 GATES, PBGA272 |
| A42MX36-BGG272A | FPGA, 54000 GATES, PBGA272 |
| A42MX36-CQ208A | FPGA, 54000 GATES, CQFP208 |
| A42MX36-CQ256A | FPGA, 54000 GATES, CQFP256 |
| A42MX36-1RQ208I | FPGA, 2438 CLBS, 36000 GATES, 91 MHz, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A40MX04-PLG68I | 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| A40MX04-PLG68M | 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 68PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 57 I/O 68PLCC 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC |
| A40MX04-PLG84 | 功能描述:IC FPGA 69I/O 84PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計:226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） |
| A40MX04-PLG84A | 功能描述:IC FPGA MX SGL CHIP 6K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| A40MX04-PLG84I | 功能描述:IC FPGA MX SGL CHIP 6K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
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