參數(shù)資料
型號(hào)： A42MX16-1CQ100M
廠商： Electronic Theatre Controls, Inc.
英文描述： IC I2C PROG PENTA ULDO 20-MLP
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 102/120頁
文件大?。?/td> 854K
代理商： A42MX16-1CQ100M
82
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
If the “ATA6289” is combined with ATA5756/ATA5757 as stacked die the pins PD5/T2O1 and
PD6/T2O2 are internally bonded with the “ASK” - and “FSK” - pins of ATA5756/ATA5757
respectively, see Figure 2-2 on page 4. So you can use the SSI of the Timer2 modulator stage to
modulate the ATA5756/ATA5757 (ASK - or FSK - modulation).
The Timer2 Compare Register (T2COR) and Timer2 Input Capture Register (T2ICR) are all
16-bit registers. Special procedures must be followed when accessing the 16-bit registers.
These procedures are described in the Section 3.13.2 “Accessing 16-bit Registers” on page 70.
The Timer2 control/mode registers (T2CRA, T2CRB, T2MRA, T2MRB, T2MDR) are 8-bit regis-
ters and have no CPU access restrictions.
The comparator output is controlled by a control register (T2CRA) and contains mask bits for the
actions (counter reset, output toggle, timer interrupt) which can be triggered by a compare match
event or the counter overflow. This architecture enables the timer for various modes.
The functions of the output modulator are controlled by two registers (T2MRB, T2MDR). The SSI
transmit data buffer register (TXB) and the SSI Receive data buffer (RXB) register share the
same I/O address referred to the SSI data register (T2MDR). The modes of Timer2 operations
and also the modulator I/O pins are controlled by the T2MRB register.
Interrupt requests (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register
(T2IFR). All interrupts are individually masked with the Timer Interrupt Mask register (T2IMR).
The counter2 input clock (CL2) can be supplied via the I/O Clock (CLK
I/O), the external input
clock (T2I), the external input clock (T3I), the Timer0 output clock (CLK
T0), the Timer1 output
clock (CLK
T1), the Timer3 output clock (CLKT3), the output clock of the Sensor Interface Block
(SENO) or the Timer clock (CLT).
The Output Compare Registers (T2COR) is compared with the Timer/Counter value at all time.
The result of the compare can be used by the modulator stage to generate a PWM or variable
frequency output on the two selectable modulator output pins (T2O1/T2O2).
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined
by either the T2MRA Register. The Timer2 has three selectable fixed TOP values.
3.13.5.1
Definitions
The following definitions are used extensively throughout the section:
The Timer2 Compare Data Values
16-bit compare register (T2COR) data value range:
m = y +1
-->
0
≤ y ≤ 65535
Three different fixed TOP data values:
n = 0x00FF, 0x01FF or 0x03FF
Table 3-36.
Definitions
Name
Description
MAX
The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
TOP
The counter reaches the TOP when it becomes equal to the highest value defined by
the fixed TOP values: 0x00FF, 0x01FF, or 0x03FF. The assignment is dependent of
the mode of operation.
相關(guān)PDF資料
PDF描述
A42MX16-1PL100 40MX and 42MX FPGA Families
A42MX16-1PL100A IC TVS BI-DIR 5V 350W SOD-323
A42MX16-1PL100B 40MX and 42MX FPGA Families
A42MX16-1PL100ES 40MX and 42MX FPGA Families
A42MX16-1PL100I 40MX and 42MX FPGA Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-1PL100 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A42MX16-1PL100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1PL100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1PL100ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A42MX16-1PL100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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