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參數(shù)資料
| 型號： | A42MX16-1CQ100M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | IC I2C PROG PENTA ULDO 20-MLP |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 115/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-1CQ100M |
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94
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Data Modes
There are two combinations of SCLK polarity with respect to the serial data, which are deter-
mined by the control bit T2CPOL (see Figure 3-36 on page 93). To ensure sufficient time for
data signal to stabilize it is recommended for external peripheral device to sample SO/SI with the
opposite edge that is used to shift out.
Bit 5 - Res: Reserved Bit
This bit is reserved bit at the ATA6289 and will always read as zero.
Bit 4 - T2TOP: Timer2 Toggle Output Preset Bit
The T2TOP bit must be written to logic one for set the toggle flip-flop, and if the T2TOP bit is
written to logic zero, toggle flip-flop is reset. This bit allows the programmer to preset the toggle
output flip-flop in the modulator of the Timer2.
Note:
If T2E = '1', no output preset is possible
Bits 3..0 - T2M3..0: Timer2 Mode Bits 3 - 0
The T2M[3..0] bits select the modes of theTimer2 and additional the configuration of the modula-
tor I/O-pins (T2O1, T2O2 and SDIN) as shown in Table 3-41.
Table 3-41.
Timer2 Mode Bit Description
Mode T2M3 T2M2 T2M1 T2M0 Timer2 Mode
Timer2 Modulator
I/O-pins
T2O1(1) T2O2(1) SDIN(1)
1
0
Timer/Counter Mode
PD5
PD6
PD7
2
0
1
Toggle Mode
M2
PD6
PD7
3
0
1
0
Toggle Mode
PD5
M2
PD7
40
0
1
PWM Mode
M2
PD6
PD7
50
1
0
PWM Mode
PD5
M2
PD7
60
1
0
1
Modulator Mode with SSI (ASK -
modulation of ATA5756/ATA57575(2))
SO
PD6
PD7
70
1
0
Modulator Mode with SSI (FSK -
modulation of ATA5756/ATA5757(2))
PD5
SO
PD7
8
0
1
SSI Transmit Mode
SO
SCLK
PD7
9
1
0
SSI Transmit Mode
SCLK
SO
PD7
10
1
0
1
SPI Mode
SO
SCLK
SI
11
1
0
1
0
Capture Mode
PD5
M2
PD7
12
1
0
1
Capture Mode
M2
PD6
PD7
13
11
00
Sensor Measurement Mode together with
Timer3
PD5
PD6
PD7
14
11
01
Reserved
PD5
PD6
PD7
15
11
10
Reserved
PD5
PD6
PD7
16
11
Reserved
PD5
PD6
PD7
Notes:
1. General Port I/O: PD5, PD6, PD7
Alternate port function:
M2
→ Output signal of the T2 (toggle flip-flop)
SO
→ SSI serial data output
SI
→ SSI serial data input
SCLK
→ SSI clock
2. As Atmel ATA6285/ATA6286 you can modulate the Atmel ATA5756/ATA5757 in these modes
相關PDF資料 |
PDF描述 |
|---|---|
| A42MX16-1PL100 | 40MX and 42MX FPGA Families |
| A42MX16-1PL100A | IC TVS BI-DIR 5V 350W SOD-323 |
| A42MX16-1PL100B | 40MX and 42MX FPGA Families |
| A42MX16-1PL100ES | 40MX and 42MX FPGA Families |
| A42MX16-1PL100I | 40MX and 42MX FPGA Families |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-1PL100 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PL100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PL100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PL100ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PL100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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