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參數(shù)資料
| 型號： | A42MX16-1PL100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 38/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-1PL100 |
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24
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.6.5.4
The EEPROM Control Register – EECR
Bits 7..6 - Res: Reserved Bits
These bits are reserved bits in the ATA6289 and will always read as zero.
Bits 5, 4 - EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bits setting defines which programming action will be trig-
gered when writing EEWE. It is possible to program data in one atomic operation (erase the old
value and program the new value) or to split the Erase and Write operations in two different
operations. The Programming times for the different modes are shown in Table 3-1. While
EEWE is set, any write command to EEPMn will be ignored. During reset, the EEPMn bits will be
reset to 0b00 unless the EEPROM is busy programming.
Bit 3 - EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
rupt when EEWE is cleared.
Bit 2 - EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one cause the EEPROM to be written.
When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at
the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has
been written to one by software, hardware clears the bit to zero after four clock cycles. See the
description of the EEWE bit for an EEPROM write procedure.
Bit
76
54
3
2
1
0
-
EEPM1
EEPM0
EERIE
EEMWE
EEWE
EERE
EECR
Read/Write
R
R/W
Initial Value
00
X
0
X
0
Table 3-1.
EEPROM Mode Bits
EEPM1
EEPM0
Programming Time
Operation
0
3.4ms
Erase and Write in one operation (Atomic Operation)
0
1
1.8ms
Erase Only
1
0
1.8ms
Write Only
1
-
Reserved for future use
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-1PL100A | IC TVS BI-DIR 5V 350W SOD-323 |
| A42MX16-1PL100B | 40MX and 42MX FPGA Families |
| A42MX16-1PL100ES | 40MX and 42MX FPGA Families |
| A42MX16-1PL100I | 40MX and 42MX FPGA Families |
| A42MX16-1PL100M | IC TVS BI-DIR 24V 350W SOD-323 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-1PL100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PL100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PL100ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PL100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PL100M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
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