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| 型號(hào)： | A42MX16-1PL100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 81/120頁(yè) |
| 文件大小： | 854K |
| 代理商： | A42MX16-1PL100 |
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63
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.12.3.3
Alternate Functions of Port C
The Port C pins with alternate function are shown in Table 3-25.
The alternate pin configuration on Port C:
PCINT10 - Port C, Bit 2
PCINT10, Pin Change Interrupt Source 10: The PC2 pin can serve as an external interrupt
source.
CLKO/PCINT9 - Port C, Bit 1
CLKO: Divided System Clock Output. The divided system clock can be output on the PC1 pin.
The divided system clock will be output if the CKOUT-Fuse bit is set (one), regardless of the
PORTC1 and DDC1 setting. It will also be output during reset.
PCINT9, Pin Change Interrupt Source 9: The PC1 pin can serve as an external interrupt source.
ECIN0/PCINT8 - Port C, Bit 0
ECIN0: External Clock Input 0. External system clock input 0 for the clock module on PC0 pin.
When used as a clock pin, the pin can not be used as an I/O pin. The clock will be input if the
CMM[1..0] bits are set (one), the ECINS bit is cleared (zero) and CSS bit is set (one) in the
CMCR register, regardless of the PORTC0 and DDC0 setting, and PORTC0, DDC0 and PINC0
will all read 0.
PCINT8, Pin Change Interrupt Source 8: The PC0 pin can serve as an external interrupt source.
Table 3-24.
Overriding Signals for Alternate Functions in PB3..PB0
Signal Name
PB3/MOSI/PCINT3
PB2/T2I/PCINT2
PB1/T3O/PCINT1
PB0/T3ICP/PCINT0
PUOE
SPE
× NMSTR
0
PUOV
PORT3
× NPUD
0
DDOE
SPE
× NMSTR
0
DDOV
0
PVOE
SPE
× MSTR
0
T3O ENABLE
0
PVOV
SPI MSTR OUTPUT
0
T3O
0
DIEOE
PCINT3
× PCIE0
PCINT2
× PCIE0
PCINT1
× PCIE0
PCINT0
× PCIE0
DIEOV
1
DI
PCINT3 INPUT
SPI SLAVE INPUT
PCINT2 INPUT
T2I INPUT
PCINT1 INPUT
PCINT0 INPUT
T3ICP INPUT
AIO
-
Table 3-25.
Port C Pins Alternate Functions
Port Pin
Alternate Functions
PC2
PCINT10 (Pin Change Interrupt 10)
PC1
PCINT9 (Pin Change Interrupt 9)
CLKO (Clock output pin for System clock)
PC0
PCINT8 (Pin Change Interrupt 8)
EXIN0 (External Clock input 0 pin)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-1PL100A | IC TVS BI-DIR 5V 350W SOD-323 |
| A42MX16-1PL100B | 40MX and 42MX FPGA Families |
| A42MX16-1PL100ES | 40MX and 42MX FPGA Families |
| A42MX16-1PL100I | 40MX and 42MX FPGA Families |
| A42MX16-1PL100M | IC TVS BI-DIR 24V 350W SOD-323 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-1PL100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PL100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PL100ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PL100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-1PL100M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
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