參數資料
型號: A42MX16-1PL100
廠商: Electronic Theatre Controls, Inc.
英文描述: 40MX and 42MX FPGA Families
中文描述: 40MX和42MX FPGA系列
文件頁數: 72/120頁
文件大?。?/td> 854K
代理商: A42MX16-1PL100
55
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.12.2
Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 3-22 shows a func-
tional description of one I/O-port pin, here generically called Pxn.
Figure 3-22. General Digital I/O(1)
WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. CLK
I/O,
SLEEP, and PUD are common to all ports.
3.12.2.1
Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in Section
I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O
address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
D
0
1
Q
WRx
RRx
WPx
Pnx
CLR
RESET
Synchronizer
D
ATA
B
U
S
PORTxn
Q
L
D
Q
D
Q
PINxn
RESET
RPx
PULLUP DISABLE
WDx:
WRITE DDRx
PUD:
I/O CLOCK
WRx:
WRITE PORTx
WPx:
WRITE PINx
RPx:
READ PINx
RRx:
READ PORTx
SLEEP CONTROL
RDx:
READ DDRx
SLEEP:
RDx
CLK
I/O
CLK:
I/O
SLEEP
PUD
WDx
D
Q
CLR
DDxn
Q
相關PDF資料
PDF描述
A42MX16-1PL100A IC TVS BI-DIR 5V 350W SOD-323
A42MX16-1PL100B 40MX and 42MX FPGA Families
A42MX16-1PL100ES 40MX and 42MX FPGA Families
A42MX16-1PL100I 40MX and 42MX FPGA Families
A42MX16-1PL100M IC TVS BI-DIR 24V 350W SOD-323
相關代理商/技術參數
參數描述
A42MX16-1PL100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1PL100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1PL100ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A42MX16-1PL100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1PL100M 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families