參數(shù)資料
型號(hào)： A42MX16-1PL100M
廠商： Electronic Theatre Controls, Inc.
英文描述： IC TVS BI-DIR 24V 350W SOD-323
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 109/120頁
文件大?。?/td> 854K
代理商： A42MX16-1PL100M
89
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.13.5.8
Timer2 Control Register B – T2CRB
Bits 7..1 - Res: Reserved Bits
These bits are reserved bits in the ATA6289 and will always read as zero.
Bit 0 - T2SCE: Timer2 Software Capture Enable Bit
The T2SCE bit must be written to logic one to generate a software capture event. The T2SCE bit
is cleared after the counter value is saved in the capture register. The Timer2 counter value is
readable via its capture register during run time.
3.13.5.9
Timer2 Modulator Data Register – T2MDR
The modulator Transmit Data Buffer Register and the modulator Receive Data Buffer Register
shares the same I/O address labeled as modulator Data Register or T2MDR. The Transmit Data
Buffer Register (TXB) will be the destination for the data written to the T2MDR Register location.
Reading the T2MDR Register location will return the contents of the Receive Data Buffer Regis-
ter (RXB).
3.13.5.10
Timer2 Input Capture Register – T2ICR
The Input Capture Register is updated with the counter value (T2CNT) each time an event
occurs on the T2ICP pin, or Timer1 output clock CLK
T1, or after a software capture event is gen-
erated with the T2SCE bit.
The Input Capture Register is a 16-bit register. To ensure that both the high and low bytes are
read simultaneously when the CPU accesses these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all 16-bit regis-
Bit
7
654
32
10
-
T2SCE
T2CRB
Read/Write
RR
R
R/W
Initial Value
0
000
00
Bit
76
54
32
10
T2MDR [7..0]
T2MDR (read)
T2MDR [7..0]
T2MDR (write)
Read/Write
R/W
Initial Value
00
Bit
76
54
32
10
T2ICRH [15..8]
T2ICRH
T2ICRL [7..0]
T2ICRL
Read/Write
RR
Initial Value
00
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-1PL84 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A42MX16-1PL84I 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A42MX16-1PL84M 制造商:Microsemi Corporation 功能描述:FPGA 42MX Family 24K Gates 608 Cells 119MHz/198MHz 0.45um Technology 3.3V/5V 84-Pin PLCC 制造商:Microsemi Corporation 功能描述:FPGA 24K GATES 608 CELLS 119MHZ/198MHZ 0.45UM 3.3V/5V 84PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 72 I/O 84PLCC 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC
A42MX16-1PLG84 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A42MX16-1PLG84I 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
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