參數(shù)資料
型號(hào): A42MX16-1PL100M
廠商: Electronic Theatre Controls, Inc.
英文描述: IC TVS BI-DIR 24V 350W SOD-323
中文描述: 40MX和42MX FPGA系列
文件頁數(shù): 21/120頁
文件大小: 854K
代理商: A42MX16-1PL100M
117
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.14.1.5
SPI Data Register – SPDR
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-
ter causes the Shift Register Receive buffer to be read.
3.14.2
Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure
3-54 and Figure 3-55 on page 118. Data bits are shifted out and latched in on opposite edges of
the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by sum-
Figure 3-54. SPI Transfer Format with CPHA = 0
Bit
765
432
10
SPDR[7..0]
SPDR
Read/Write
R/W
Initial Value
X
XXX
X
Undefined
Table 3-50.
CPOL/CHPA Functionality
Leading Edge
Trailing Edge
SPI Mode
CPOL = 0, CPHA = 0
Sample(Rising)
Setup(Falling)
0
CPOL = 0, CPHA = 1
Setup(Rising)
Sample(Falling)
1
CPOL = 1, CPHA = 0
Sample(Falling)
Setup(Rising)
2
CPOL = 1, CPHA = 1
Setup(Falling)
Sample(Rising)
3
LSB
MSB
Bit 1
Bit 6
Bit 2
Bit 5
Bit 3
Bit 4
Bit 3
Bit 5
Bit 2
Bit 6
Bit 1
MSB
LSB
MSB first (DORD = 0)
LSB first (DORD =1)
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SS
SAMPLE -
MOSI/MISO
MISO - PIN
MOSI - PIN
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