- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄298744 > A42MX16-2VQ100A (Electronic Theatre Controls, Inc.) 40MX and 42MX FPGA Families PDF資料下載
參數(shù)資料
| 型號： | A42MX16-2VQ100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 10/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-2VQ100A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁
107
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.13.7.6
Timer3 Interrupt Flag Register – T3IFR
Bits 7..4 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 3 - T3ICF: Timer3 Input Capture Flag Bit
This flag is set (one) when a capture event occurs on the T3ICP pin and indicating that the
Timer3/Counter3 value has been transferred to the capture register (T3ICR). If the I-bit in SREG
and the T3CPIM bit is set (one) at T3IMR register, the MCU will jump to the corresponding Inter-
rupt Vector. T3ICF is automatically cleared when the interrupt routine is executed. Alternatively,
T3ICP can be cleared by writing a logic one.
Bit 2 - T3COBF: Timer3 COmpare B Flag Bit
This flag is set (one) if the Timer3/Counter3 value (T3CNT) matches with the Compare Register
B value. If the I-bit in SREG and the T3CBIM bit is set (one) at T3IMR register, the MCU will
jump to the corresponding Interrupt Vector. The flag (T3COBF) is cleared when the interrupt rou-
tine is executed. Alternatively, the flag can be cleared by writing a logical one.
Bit 1 - T3COAF: Timer3 COmpare A Flag Bit
This flag is set (one) if the Timer3/Counter3 value (T3CNT) matches with the Compare Register
A value. If the I-bit in SREG and the T3CAIM bit is set (one) at T3IMR register, the MCU will
jump to the corresponding Interrupt Vector. The flag (T3COAF) is cleared when the interrupt rou-
tine is executed. Alternatively, the flag can be cleared by writing a logical one.
Bit 0 - T3OFF: Timer3 OverFlow Flag Bit
This flag is set (one) if the Timer3/Counter3 overflow (OVF) occurs. If the I-bit in SREG and the
T3OIM bit is set (one) at T3IMR register, the MCU will jump to the corresponding Interrupt Vec-
tor. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be
cleared by writing a logical one.
Bit
765
43210
-
T3ICF
T3COBF T3COAF
T3OFF
T3IFR
Read/Write
RRRR
R/W
Initial Value
000
10000
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-2VQ100B | 40MX and 42MX FPGA Families |
| A42MX16-2VQ100ES | 40MX and 42MX FPGA Families |
| A42MX16-3PQ100B | 40MX and 42MX FPGA Families |
| A42MX16-3BG100 | 40MX and 42MX FPGA Families |
| A42MX16-3PL100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-2VQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2VQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2VQ100I | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX16-2VQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2VQG100 | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。