參數(shù)資料
型號: A42MX16-PL84I
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場可編程門陣列(FPGA)
文件頁數(shù): 19/116頁
文件大?。?/td> 3110K
代理商: A42MX16-PL84I
v5.0
19
40MX and 42MX FPGA Families
Active Power Component
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency-dependent and a function of the logic and the
external I/O. Active power dissipation results from charging
internal
chip
capacitances
unprogrammed antifuses, module inputs, and module
outputs, plus external capacitance due to PC board traces
and load device inputs. An additional component of the
active power dissipation is the totem pole current in the
CMOS transistor pairs. The net effect can be associated
with an equivalent capacitance that can be combined with
frequency and voltage to represent active power dissipation.
of
the
interconnect,
Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by
the equation:
Power (μW) = C
EQ
* V
CCA2
* F
where:
C
EQ
= Equivalent capacitance expressed in picofarads
(pF)
V
CCA
= Power supply in volts (V)
F
= Switching frequency in megahertz (MHz)
Equivalent capacitance is calculated by measuring
I
CC
active at a specified frequency and voltage for each
circuit component of interest. Measurements have been
made over a range of frequencies at a fixed value of
V
CC
.
Equivalent capacitance is frequency-independent, so the
results can be used over a wide range of operating
conditions. Equivalent capacitance values are shown below.
(1)
C
EQ
Values for Actel MX FPGAs
Modules (C
EQM
)
Input Buffers (C
EQI
)
Output Buffers (C
EQO
)
Routed Array Clock Buffer Loads (C
EQCR
)
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic
must be known. The equation below shows a piece-wise
linear summation over all components.
Power = V
CCA2
* [(m x
C
EQM
* f
m
)
Modules
+
(n *
C
EQI
* f
n
)
Inputs
+ (p * (
C
EQO
+ C
L
) * f
p
)
outputs
+
0.5 * (q
1
*
C
EQCR
* f
q1
)
routed_Clk1
+ (r
1
* f
q1
)
routed_Clk1
+
0.5 * (q
2
*
C
EQCR
* f
q2
)
routed_Clk2
+ (r
2
* f
q2
)
routed_Clk2
3.5
6.9
18.2
1.4
(2)
where:
m
n
p
q
1
Fixed Capacitance Values
for MX FPGAs (pF)
=Number of logic modules switching at frequency f
m
=Number of input buffers switching at frequency f
n
=Number of output buffers switching at frequency f
p
=Number of clock loads on the first routed array
clock
=Number of clock loads on the second routed array
clock
=lFixed capacitance due to first routed array clock
=Fixed capacitance due to second routed array
clock
C
EQM
=Equivalent capacitance of logic modules in pF
C
EQI
=Equivalent capacitance of input buffers in pF
C
EQO
=Equivalent capacitance of output buffers in pF
C
EQCR
=Equivalent capacitance of routed array clock in pF
C
L
=Output load capacitance in p
f
m
=Average logic module switching rate in MHz
f
n
=Average input buffer switching rate in MHz
f
p
=Average output buffer switching rate in MHz
f
q1
=Average first routed array clock rate in MHz
f
q2
=Average second routed array clock rate in MHz
q
2
r
1
r
2
Device Type
r
1
routed_Clk1
r
2
routed_Clk2
A40MX02
41.4
N/A
A40MX04
68.6
N/A
A42MX09
118
118
A42MX16
165
165
A42MX24
185
185
A42MX36
220
220
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