參數(shù)資料
型號: A42MX24-3PQ160I
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場可編程門陣列(FPGA)
文件頁數(shù): 54/116頁
文件大?。?/td> 3110K
代理商: A42MX24-3PQ160I
40MX and 42MX FPGA Families
54
v5.0
A42MX16 Timing Characteristics (Nominal 5.0V Operation)
(continued)
(Worst-Case Commercial Conditions, V
CC
= 4.75V, T
J
= 70
°
C)
‘–
3
Speed
‘–
2
Speed
‘–
1
Speed
Std
Speed
‘–
F
Speed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
TTL Output Module Timing
1
t
DLH
Data-to-Pad HIGH
2.5
2.8
3.2
3.7
5.2
ns
t
DHL
Data-to-Pad LOW
3.0
3.3
3.7
4.4
6.1
ns
t
ENZH
Enable Pad Z to HIGH
2.7
3.0
3.4
4.0
5.6
ns
t
ENZL
Enable Pad Z to LOW
3.0
3.3
3.8
4.4
6.2
ns
t
ENHZ
Enable Pad HIGH to Z
5.4
6.0
6.8
8.0
11.2
ns
t
ENLZ
Enable Pad LOW to Z
5.0
5.6
6.3
7.4
10.4
ns
t
GLH
G-to-Pad HIGH
2.9
3.2
3.6
4.3
6.0
ns
t
GHL
G-to-Pad LOW
2.9
3.2
3.6
4.3
6.0
ns
t
LCO
I/O Latch Clock-to-Out (Pad-to-Pad),
64 Clock Loading
5.7
6.3
7.1
8.4
11.9
ns
t
ACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
d
TLH2
d
THL2
CMOS Output Module Timing
1
Capacitive Loading, LOW to HIGH
0.03
0.03
0.03
0.04
0.06
ns/pF
Capacitive Loading, HIGH to LOW
0.04
0.04
0.04
0.05
0.07
ns/pF
t
DLH
Data-to-Pad HIGH
3.2
3.6
4.0
4.7
6.6
ns
t
DHL
Data-to-Pad LOW
2.5
2.7
3.1
3.6
5.1
ns
t
ENZH
Enable Pad Z to HIGH
2.7
3.0
3.4
4.0
5.6
ns
t
ENZL
Enable Pad Z to LOW
3.0
3.3
3.8
4.4
6.2
ns
t
ENHZ
Enable Pad HIGH to Z
5.4
6.0
6.8
8.0
11.2
ns
t
ENLZ
Enable Pad LOW to Z
5.0
5.6
6.3
7.4
10.4
ns
t
GLH
G-to-Pad HIGH
5.1
5.6
6.4
7.5
10.5
ns
t
GHL
G-to-Pad LOW
5.1
5.6
6.4
7.5
10.5
ns
t
LCO
I/O Latch Clock-to-Out (Pad-to-Pad),
64 Clock Loading
5.7
6.3
7.1
8.4
11.9
ns
t
ACO
Array Clock-to-Out (Pad-to-Pad),
64 Clock Loading
8.0
8.9
10.1
11.9
16.7
ns
d
TLH2
d
THL2
Notes:
1.
2.
Capacitive Loading, LOW to HIGH
0.03
0.03
0.03
0.04
0.06
ns/pF
Capacitive Loading, HIGH to LOW
0.04
0.04
0.04
0.05
0.07
ns/pF
Delays based on 35 pF loading.
Slew rates measured from 10% to 90% V
CCI
.
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