參數(shù)資料
型號: A42MX24-3PQ160I
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場可編程門陣列(FPGA)
文件頁數(shù): 56/116頁
文件大?。?/td> 3110K
代理商: A42MX24-3PQ160I
40MX and 42MX FPGA Families
56
v5.0
A42MX16 Timing Characteristics (Nominal 3.3V Operation)
(continued)
(Worst-Case Commercial Conditions, V
CC
= 3.0V, T
J
= 70
°
C)
‘–
3
Speed
‘–
2
Speed
‘–
1
Speed
Std
Speed
‘–
F
Speed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
t
INYH
Pad-to-Y HIGH
1.5
1.6
1.9
2.2
3.1
ns
t
INYL
Pad-to-Y LOW
1.1
1.3
1.4
1.7
2.4
ns
t
INGH
G to Y HIGH
2.0
2.2
2.5
2.9
4.1
ns
t
INGL
Input Module Predicted Routing Delays
1
G to Y LOW
2.0
2.2
2.5
2.9
4.1
ns
t
IRD1
FO=1 Routing Delay
2.6
2.9
3.2
3.8
5.3
ns
t
IRD2
FO=2 Routing Delay
2.9
3.2
3.7
4.3
6.1
ns
t
IRD3
FO=3 Routing Delay
3.3
3.6
4.1
4.9
6.8
ns
t
IRD4
FO=4 Routing Delay
3.6
4.0
4.6
5.4
7.6
ns
t
IRD8
FO=8 Routing Delay
5.1
5.6
6.4
7.5
10.5
ns
Global Clock Network
t
CKH
Input LOW to HIGH
FO = 32
FO = 384
4.4
4.8
4.8
5.3
5.5
6.0
6.5
7.1
9.0
9.9
ns
ns
t
CKL
Input HIGH to LOW
FO = 32
FO = 384
5.3
6.2
5.9
6.9
6.7
7.9
7.8
9.2
11.0
12.9
ns
ns
t
PWH
Minimum Pulse Width
HIGH
FO = 32
FO = 384
5.7
6.6
6.3
7.4
7.1
8.3
8.4
9.8
11.8
13.7
ns
ns
t
PWL
Minimum Pulse Width
LOW
FO = 32
FO = 384
5.3
6.2
5.9
6.9
6.7
7.9
7.8
9.2
11.0
12.9
ns
ns
t
CKSW
Maximum Skew
FO = 32
FO = 384
0.5
2.2
0.5
2.4
0.6
2.7
0.7
3.2
1.0
4.5
ns
ns
t
SUEXT
Input Latch External
Set-Up
FO = 32
FO = 384
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
t
HEXT
Input Latch External Hold FO = 32
FO = 384
3.9
4.5
4.3
4.9
4.9
5.6
5.7
6.6
8.0
9.2
ns
ns
t
P
Minimum Period
FO = 32
FO = 384
7.0
7.7
7.8
8.6
8.4
9.3
9.7
10.7
16.2
17.8
ns
ns
f
MAX
Maximum Frequency
FO = 32
FO = 384
142
129
129
117
119
108
103
94
62
56
MHz
MHz
Note:
1.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
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