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參數(shù)資料
| 型號： | A42MX36-BGG272A |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 54000 GATES, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 2/76頁 |
| 文件大?。?/td> | 429K |
| 代理商： | A42MX36-BGG272A |
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MX Automotive Family FPGAs
1- 4
v2 .0
MultiPlex I/O Modules
Automotive-grade 42MX devices offer MultiPlex I/Os,
which support both 3.3V and 5.0V operations.
The MultiPlex I/O modules provide a flexible interface
between the device pins and the logic array. Figure 1-6 is
a block diagram of the 42MX I/O module. A variety of
user functions, determined by a library macro selection,
can be implemented in the module. (Refer to the Macro
Library Guide for more information.) All 42MX I/O
modules contain tri-state buffers, with input and output
latches that can be configured for input, output, or bi-
directional
operation.
Each
output
buffer
has
a
dedicated output enable control. The I/O module can be
used to latch input or output data, or both, providing a
fast set-up time. In addition, the Actel Designer Series
software tools can build a D-type flip-flop using a C-
module to register input and output signals.
Actel’s Designer Series development tools provide a
design library of I/O macro functions that can implement
all I/O configurations supported by the automotive-
grade MX FPGAs.
Routing Structure
The MX architecture uses vertical and horizontal routing
tracks to interconnect the various logic and I/O modules.
These routing tracks are metal interconnects that may be
either of continuous length or broken into pieces called
segments.
Varying
segment
lengths
allows
the
interconnect of over 90% of design tracks to occur with
only two antifuse connections. Segments can be joined
together at the ends using antifuses to increase their
lengths up to the full length of the track. All
interconnects can be accomplished with a maximum of
four antifuses.
Horizontal Routing
Horizontal channels are located between the rows of
modules and are composed of several routing tracks. The
horizontal routing tracks within the channel are divided
into one or more segments. The minimum horizontal
segment length is the width of a module pair, and the
maximum horizontal segment length is the full length of
the channel. Any segment that spans more than one-
third at the row length is considered a long horizontal
segment. A typical channel is shown in Figure 1-7. Non-
dedicated horizontal routing tracks are used to route
signal nets; dedicated routing tracks are used for global
clock networks and for power and ground tie-off
tracks.
Vertical Routing
Another set of routing tracks run vertically through the
module. There are three types of vertical tracks: input,
output, and long, which are also divided into one or
more segments. Each segment in an input track is
dedicated to the input of a particular module; each
segment in an output track is dedicated to the output of
a particular module. Long segments are uncommitted
and can be assigned during routing. Each output
segment spans four channels (two above and two
below), except near the top and bottom of the array,
where edge effects occur. Long vertical tracks contain
either one or two segments. An example of vertical
routing tracks and segments is shown in Figure 1-7.
Note: *Can be Configured as a Latch or D Flip-Flop (Using C-
Module)
Figure 1-6 42MX I/O Module
Figure 1-7 Routing Structure
G/CLK*
QD
OE
PAD
From Array
To Array
G/CLK*
QD
Vertical Routing Tracks
Antifuses
Logic
Segmented
Horizontal
Routing
Tracks
Modules
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PDF描述 |
|---|---|
| A42MX36-CQ208A | FPGA, 54000 GATES, CQFP208 |
| A42MX36-CQ256A | FPGA, 54000 GATES, CQFP256 |
| A42MX36-1RQ208I | FPGA, 2438 CLBS, 36000 GATES, 91 MHz, PQFP208 |
| A42MX36-1RQ208 | FPGA, 2438 CLBS, 36000 GATES, 91 MHz, PQFP208 |
| A42MX36-1RQG208I | FPGA, 2438 CLBS, 36000 GATES, 91 MHz, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX36-BGG272I | 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75） |
| A42MX36-BGG272M | 制造商:Microsemi Corporation 功能描述:FPGA 42MX Family 54K Gates 1184 Cells 79MHz/131MHz 0.45um Technology 3.3V/5V 272-Pin BGA 制造商:Microsemi Corporation 功能描述:FPGA 54K GATES 1184 CELLS 79MHZ/131MHZ 0.45UM 3.3V/5V 272BGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 202 I/O 272PBGA |
| A42MX36-CQ208 | 功能描述:IC FPGA MX SGL CHIP 54K 208-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75） |
| A42MX36-CQ208B | 功能描述:IC FPGA MX SGL CHIP 54K 208-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75） |
| A42MX36-CQ208M | 制造商:Microsemi Corporation 功能描述:FPGA 54K GATES 1184 CELLS 79MHZ/131MHZ 0.45UM 3.3V/5V 208CQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 176 I/O 208CQFP 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 54K 208-CQFP |
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