參數(shù)資料
型號(hào)： A42MX36-BGG272A
元件分類： FPGA
英文描述： FPGA, 54000 GATES, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 38/76頁
文件大?。?/td> 429K
代理商： A42MX36-BGG272A
MX Automotive Family FPGAs
v2.0
1-37
tGHL
G-to-Pad LOW
5.1
ns
tLSU
I/O Latch Output Set-Up
0.8
ns
tLH
I/O Latch Output Hold
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O
9.5
ns
tACO
Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O
18.5
ns
dTLH
Capacitive Loading, LOW to HIGH
0.06
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.05
ns/pF
CMOS Output Module Timing5
tDLH
Data-to-Pad HIGH
5.1
ns
tDHL
Data-to-Pad LOW
4.1
ns
tENZH
Enable Pad Z to HIGH
4.1
ns
tENZL
Enable Pad Z to LOW
4.9
ns
tENHZ
Enable Pad HIGH to Z
8.9
ns
tENLZ
Enable Pad LOW to Z
8.3
ns
tGLH
G-to-Pad HIGH
8.5
ns
tGHL
G-to-Pad LOW
8.5
ns
tLSU
I/O Latch Set-Up
0.8
ns
tLH
I/O Latch Hold
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad) 32 I/O
9.5
ns
tACO
Array Latch Clock-to-Out (Pad-to-Pad) 32 I/O
18.5
ns
dTLH
Capacitive Loading, LOW to HIGH
0.06
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.05
ns/pF
Table 1-9 A42MX24 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125°C (Continued)
‘Std’ Speed
Parameter
Description
Min.
Max.
Units
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關(guān)PDF資料
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A42MX36-CQ208A FPGA, 54000 GATES, CQFP208
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A42MX36-1RQ208 FPGA, 2438 CLBS, 36000 GATES, 91 MHz, PQFP208
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX36-BGG272I 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A42MX36-BGG272M 制造商:Microsemi Corporation 功能描述:FPGA 42MX Family 54K Gates 1184 Cells 79MHz/131MHz 0.45um Technology 3.3V/5V 272-Pin BGA 制造商:Microsemi Corporation 功能描述:FPGA 54K GATES 1184 CELLS 79MHZ/131MHZ 0.45UM 3.3V/5V 272BGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 202 I/O 272PBGA
A42MX36-CQ208 功能描述:IC FPGA MX SGL CHIP 54K 208-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A42MX36-CQ208B 功能描述:IC FPGA MX SGL CHIP 54K 208-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A42MX36-CQ208M 制造商:Microsemi Corporation 功能描述:FPGA 54K GATES 1184 CELLS 79MHZ/131MHZ 0.45UM 3.3V/5V 208CQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 176 I/O 208CQFP 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 54K 208-CQFP
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