參數(shù)資料
型號： A42MX36-BGG272A
元件分類： FPGA
英文描述： FPGA, 54000 GATES, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 36/76頁
文件大小： 429K
代理商： A42MX36-BGG272A
MX Automotive Family FPGAs
v2.0
1-35
Table 1-9 A42MX24 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125°C
‘Std’ Speed
Parameter
Description
Min.
Max.
Units
Logic Module Combinatorial Functions1
tPD
Internal Array Module Delay
2.1
ns
tPDD
Internal Decode Module Delay
2.5
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
1.4
ns
tRD2
FO=2 Routing Delay
1.7
ns
tRD3
FO=3 Routing Delay
2.2
ns
tRD4
FO=4 Routing Delay
2.6
ns
tRD5
FO=8 Routing Delay
4.2
ns
Logic Module Sequential Timing3, 4
tCO
Flip-Flop Clock-to-Output
2.2
ns
tGO
Latch Gate-to-Output
2.1
ns
tSU
Flip-Flop (Latch) Set-Up Time
0.6
ns
tH
Flip-Flop (Latch) Hold Time
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
2.5
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.7
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
5.8
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
7.6
ns
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.8
ns
tINGO
Input Latch Gate-to-Output
2.2
ns
tINH
Input Latch Hold
0.0
ns
tINSU
Input Latch Set-Up
0.8
ns
tILA
Latch Active Pulse Width
8.1
ns
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
3.2
ns
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX36-BGG272I 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
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A42MX36-CQ208B 功能描述:IC FPGA MX SGL CHIP 54K 208-CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A42MX36-CQ208M 制造商:Microsemi Corporation 功能描述:FPGA 54K GATES 1184 CELLS 79MHZ/131MHZ 0.45UM 3.3V/5V 208CQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 176 I/O 208CQFP 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 54K 208-CQFP
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