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參數(shù)資料
| 型號： | A54SX08AFG144M |
| 英文描述： | Logic IC |
| 中文描述： | 邏輯IC |
| 文件頁數(shù)： | 17/36頁 |
| 文件大?。?/td> | 833K |
| 代理商： | A54SX08AFG144M |
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v2.0
17
54SX Family FPGAs RadTolerant and HiRel
Timing Characteristics
Timing characteristics for 54SX devices fall into three
categories: family-dependent, device-dependent, and
design-dependent.
The
input
characteristics are common to all 54SX family members.
Internal routing delays are device dependent. Design
dependency means actual delays are not determined until
after placement and routing of the user
’
s design is
complete. Delay values may then be determined by using
the DirectTime Analyzer utility or performing simulation
with post-layout delays.
and
output
buffer
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most
time-critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up to
6 percent of the nets in a design may be designated as
critical, while 90 percent of the nets in a design are typical.
Long Tracks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns,
or modules. Long tracks employ three and sometimes five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically up to 6% of nets in a fully
utilized device require long tracks. Long tracks contribute
approximately 4 ns to 8.4 ns delay. This additional delay is
represented statistically in higher fanout (FO=24) routing
delays in the data sheet specifications section.
Timing Derating
54SX devices are manufactured in a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process variations. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case processing.
Maximum timing parameters reflect minimum operating
voltage, maximum operating temperature, and worst-case
processing.
Register Cell Timing Characteristics
Flip-Flops
(Positive edge triggered)
D
CLK
CLR
Q
D
CLK
Q
CLR
t
HPWH
,
t
RPWH
t
WASYN
t
HD
t
SUD
t
HP
t
HPWL
,
t
RPWL
t
RCO
t
CLR
PRESET
t
PRESET
PRESET
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A54SX08-FG144 | Field Programmable Gate Array (FPGA) |
| A54SX08-FG144I | Field Programmable Gate Array (FPGA) |
| A54SX08-PL84 | Field Programmable Gate Array (FPGA) |
| A54SX08-PL84I | Field Programmable Gate Array (FPGA) |
| A54SX08-PL84M | Field Programmable Gate Array (FPGA) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A54SX08A-FG208 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SX-A Family FPGAs |
| A54SX08AFG208A | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs |
| A54SX08A-FG208A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SX-A Family FPGAs |
| A54SX08A-FG208B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SX-A Family FPGAs |
| A54SX08AFG208I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs |
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