參數(shù)資料
型號(hào)： A54SX08AFG144M
英文描述： Logic IC
中文描述： 邏輯IC
文件頁(yè)數(shù)： 23/36頁(yè)
文件大?。?/td> 833K
代理商： A54SX08AFG144M
v2.0
23
54SX Family FPGAs RadTolerant and HiRel
A54SX32 Timing Characteristics
(continued)
(Worst-Case Military Conditions, V
CCR
= 4.75V, V
CCA,
V
CCI
= 3.0V, T
J
= 125
°
C)
I/O Module
–
TTL Output Timing
1
‘–
1
’
Speed
‘
Std
’
Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
t
DLH
t
DHL
t
ENZL
t
ENZH
t
ENLZ
t
ENHZ
d
TLH
d
THL
Data-to-Pad LOW to HIGH
2.8
3.3
ns
Data-to-Pad HIGH to LOW
2.8
3.3
ns
Enable-to-Pad, Z to L
2.3
2.8
ns
Enable-to-Pad, Z to H
2.8
3.3
ns
Enable-to-Pad, L to Z
4.5
5.2
ns
Enable-to-Pad, H to Z
2.2
2.6
ns
Delta LOW to HIGH
0.05
0.06
ns/pF
Delta HIGH to LOW
0.05
0.08
ns/pF
Dedicated (Hard-Wired) Array Clock Network
t
HCKH
Input LOW to HIGH
(Pad to R-Cell Input)
1.7
2.0
ns
t
HCKL
Input HIGH to LOW
(Pad to R-Cell Input)
1.9
2.2
ns
t
HPWH
t
HPWL
t
HCKSW
t
HP
f
HMAX
Minimum Pulse Width HIGH
2.1
2.4
ns
Minimum Pulse Width LOW
2.1
2.4
ns
Maximum Skew
0.4
0.4
ns
Minimum Period
4.2
4.8
ns
Maximum Frequency
240
205
MHz
Routed Array Clock Networks
t
RCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
2.4
2.9
ns
t
RCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
2.7
3.1
ns
t
RCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
2.9
3.3
ns
t
RCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
2.9
3.5
ns
t
RCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
2.8
3.3
ns
t
RCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
2.9
3.5
ns
t
RPWH
t
RPWL
t
RCKSW
t
RCKSW
t
RCKSW
Note:
1.
Min. Pulse Width HIGH
3.1
3.7
ns
Min. Pulse Width LOW
3.1
3.7
ns
Maximum Skew (Light Load)
0.6
0.8
ns
Maximum Skew (50% Load)
0.8
0.9
ns
Maximum Skew (100% Load)
0.8
0.9
ns
Delays based on 35pF loading, except t
ENZL
and t
ENZH
. For t
ENZL
and t
ENZH
the loading is 5 pF.
相關(guān)PDF資料
PDF描述
A54SX08-FG144 Field Programmable Gate Array (FPGA)
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