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參數資料
| 型號： | a8255 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Peripheral Interface Adapter(可編程外圍接口適配器) |
| 中文描述： | 可編程外圍接口適配器（可編程外圍接口適配器） |
| 文件頁數： | 2/13頁 |
| 文件大?。?/td> | 250K |
| 代理商： | A8255 |
46
Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Table 1
describes the input and output ports of the
a8255
.
Table 1. a8255 Ports
Name
Type
Polarity
Description
clk
Input
Input
–
Clock.
Chip select. When
and write transactions to internal registers are possible.
Read control. When
nrd
is asserted and the
transactions from internal registers are possible.
Write control. When
nwr
is asserted and the
transactions to internal registers are possible.
Reset. Initializes the control and port C output registers, and sets the
port A, B, and C registers to input mode.
Register address bus. This bus selects one of the internal registers.
Data input bus. The CPU writes data to the internal control, port A,
port B, or port C register via the
din[7..0]
Port A input data bus.
Port B input data bus.
Port C input data bus.
Port A data enable. Output enable for the port A output data bus.
Port B data enable. Output enable for the port B output data bus.
Data output bus. The CPU reads data from the internal control,
port A, port B, or port C register via the
Port A output data bus.
Port B output data bus.
Port C data enable bus. Output enable for each bit of the port C
output data bus.
Port C output data bus.
ncs
Low
ncs
is asserted, the
a8255
is selected and read
nrd
Input
Low
a8255
is selected, read
nwr
Input
Low
a8255
is selected, write
reset
Input
High
a[1..0]
Input
Input
High
High
din[7..0]
bus.
pain[7..0]
Input
Input
Input
Output
Output
Output
High
High
High
High
High
High
pbin[7..0]
pcin[7..0]
paen
pben
dout[7..0]
dout[7..0]
bus.
paout[7..0]
Output
Output
Output
High
High
High
pbout[7..0]
pcen[7..0]
pcout[7..0]
Output
High
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