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參數(shù)資料
| 型號(hào)： | a8255 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Peripheral Interface Adapter(可編程外圍接口適配器) |
| 中文描述： | 可編程外圍接口適配器（可編程外圍接口適配器） |
| 文件頁(yè)數(shù)： | 6/13頁(yè) |
| 文件大?。?/td> | 250K |
| 代理商： | A8255 |
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Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Port A, B & C Registers
Depending on the configured input and output directions that are set in
the control register, the microprocessor either reads or writes data
to/from the port A, B, or C registers. Ports A and B have separate input
and output registers.
In mode 0, the port C register functions identically to the port A and B
registers. In modes 1 and 2, the port C register has a specialized role; a
write to port C has no effect—the register bits must be altered individually
using the port C bit set/reset format. Reading the port C status bits in
modes 1 or 2 provides the CPU with the status of the control signals and
flags, as shown in
Tables 5 through 7
. However, the modes and port
directions can be mixed in more combinations than these tables illustrate.
Notes:
(1)
(2)
These bits are defined in
Table 9
.
Bits 6 and 7 effectively operate in mode 0. The I/O direction is dependent on bit 3
of the control register.
Table 5. Port C Status Bits with Ports A & B in Mode 1 Input
Note (1)
Bit
Signal
Description
0
1
2
3
4
5
6
7
intrb
Port B interrupt request
Port B input buffer full flag
Port B interrupt enable
Port A interrupt request
Port A interrupt enable
Port A input buffer full flag
Note (2)
Note (2)
ibfb
inteb
intra
intea
ibfa
I/O
I/O
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