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參數(shù)資料
| 型號： | a8255 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Peripheral Interface Adapter(可編程外圍接口適配器) |
| 中文描述： | 可編程外圍接口適配器（可編程外圍接口適配器） |
| 文件頁數(shù)： | 8/13頁 |
| 文件大小： | 250K |
| 代理商： | A8255 |
52
Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Mode 0: Basic Input/Output
Mode 0 is used to perform simple reads or writes of relatively static
signals, such as switches or status displays. Port A, port B, port C (upper),
and port C (lower) can be independently configured as inputs or outputs
without requiring handshake signals. Data written by the CPU to a port
configured as an output is registered; data read by the CPU from a port
configured as an input is not registered.
Mode 1: Strobed Input/Output
Mode 1 is used to perform reads or writes of data controlled by handshake
signals. Ports A and B are the data ports, configured independently as
either inputs or outputs. Port C provides the three handshaking signals
for each of the data ports. Both input and output data are registered.
Table 8
shows how the handshaking signals are configured for mode 1
input.
Table 8. Handshaking Signal Configuration (Mode 1 Input)
Name
Signal
Type
Description
nstb
Input
Output
Strobe. Enable for input register.
Input buffer full flag. When set, indicates that data has been
loaded into the input register. Set by
nstb
going low, and
reset by the rising edge of the
nrd
input.
Interrupt request. Can be used as the interrupt signal to the
CPU. Set on the rising edge of
nstb
when
inte
is high.
Reset by the falling edge of
nrd
.
Interrupt enable. Set by bit set to PC4 for port A and PC2 for
port B.
ibf
intr
Output
inte
Internal
control
bit
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