參數(shù)資料
型號: ACE9030
廠商: Mitel Networks Corporation
英文描述: Radio Interface and Twin Synthesiser(用于蜂窩式電話的無線電接口電路和雙合成器)
中文描述: 無線接口和雙合成器(用于蜂窩式電話的無線電接口電路和雙合成器)
文件頁數(shù): 19/39頁
文件大?。?/td> 379K
代理商: ACE9030
ACE9030
19
8·064 MHz Oscillator
Fig. 16 OSC8 Block Diagram
Table 2
Command
Data D2 D1 D0
1 0 0
0 1 1
1 0 1
1 1 0*
* Power up default
Crystal
frequency
12·8 MHz
14·85 MHz
14·85 MHz
15·36 MHz
Crystal
divider
÷
100
÷
825
÷
337
÷
120
PLL comp.
freq. (kHz)
128
18
44·065281
128
OSC8
divider
÷
63
÷
448
÷
183
÷
63
Exact CLK8
output (MHz)
8·064
8·064
8·0639466
8·064
Error
(ppm)
0
0
–7
0
An 8·064 MHz oscillator OSC8 is provided to drive the
ACE9050 System Controller through pin CLK8. ACE9050
further drives the ACE9040 Audio Processor and the CL bus
clock via a
÷
8 divider. OSC8 is locked to the crystal oscillator
by a phase locked loop with an external filter on pin C8B.
This loop can be programmed by a Set-up command to
give the correct output frequency with any of the normally used
crystals. Note that the same Set-up command uses DATA1 bit
D
for the lock logic and bits D
7
and D
6
for the Discriminator
programming:
DATA1
DATA2
10xxxxxx
DATA3
xx1xxx00
xxxxx D
2
D
1
D
0
where D
2
D
D
act as in table 2. At power-on reset the setting
is D
D
D
= 110, the values for a 15·36 MHz crystal, so that
the microcontroller is never clocked too fast with any of the
crystals and can then send the Set-up message to set D
2
D
1
D
0
to the correct levels.
With a 14·85 MHz crystal it is not possible to both use a
high comparison frequency and get the exact 8·064 MHz
output, so two options are provided. The lower comparison
frequency will give the output exactly correct but will need
larger capacitors in the loop filter and the higher option allows
smaller capacitors and can improve close-in phase noise by
having a larger loop bandwidth, but gives a very small fre-
quency error - this error should have no effect in a practical
cellular terminal.
A Sleep command will not change the status of OSC8; if
enabled it will remain active when put into Sleep mode and
when returning to Normal mode. If the OSC8 oscillator is not
required it can be switched off by a Set-up command:
DATA1
xxxxxxxx
DATA2
10xxxxx D
0
DATA3
xxxxxx00
where DATA2 bit D0 at LOW gives OSC8 OFF or DATA2 bit
D
0
at HIGH gives OSC8 ON.
To allow for design and manufacturing tolerances the
VCO can be trimmed by two set-up commands, each of which
loads a 6 bit value in DATA1 into a control register. One sets
frequency “Range” (effectively the VCO gain but also with an
effect on the centre frequency):
DATA1
DATA2
10x1xxxx
DATA3
xxxxxx00
xx D
5
D
4
D
3
D
2
D
1
D
0
The default values loaded by the power-on reset are
Offset = 0A
and Range = 21
and were chosen to help
ensure that the output clock on CLK8 does not run faster than
8·064 MHz while better values are to be loaded. These default
values can usually be left unchanged for normal operation.
The output of the phase comparator charge pump is on
pin C8B so that an external loop filter can be connected. This
loop filter then drives the VCO control voltage, also through
DATA1
DATA2
10xx1xxx
DATA3
xxxxxx00
xx D
5
D
4
D
3
D
2
D
1
D
0
The other sets frequency “Offset” (effectively the VCO
centre frequency but also with an effect on the gain):
RANGE &
OFFSET
FROM BUS
RATIO, FROM BUS
8.064 MHz OUTPUT FREQUENCY
PHASE
DETECTOR
C8B
RATIO, FROM BUS
: 63/183/448
EXTERNAL
LOOP
FILTER
CLK8
CHARGE
PUMPS
DOWN
UP
50
μ
A
50
μ
A
φ
φ
: 100/337/825
CRYSTAL
FREQUENCY
(XO)
VCO
相關(guān)PDF資料
PDF描述
ACE9030 Radio Interface and Twin Synthesiser
ACE9040 Audio Processor Advance Information
ACE9050 System Controller and Data Modem(為蜂窩式手機提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器)
ACE9050 System Controller and Data Modem Advance Information
ACFA-450 AM CERAMIC FILTERS
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