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參數(shù)資料
| 型號： | ACTS10K |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened Triple Three-Input NAND Gate |
| 中文描述： | 輻射加固三三輸入與非門 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 112K |
| 代理商： | ACTS10K |
5
ACTS10MS
Spec Number
518823
Propagation Delay Timing Diagram and Load Circuit
Intersil - Space Products MS Screening
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM)
Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull Method 2023
100% Internal Visual Inspection Method 2010
100% Temperature Cycling Method 1010 Condition C
(-65
o
to +150
o
C)
100% Constant Acceleration
100% PIND Testing
100% External Visual Inspection
100% Serialization
100% Initial Electrical Test
100% Static Burn-In 1 Method 1015, 24 Hours at +125
o
C Min
100% Interim Electrical Test 1 (Note 1)
100% Static Burn-In 2 Method 1015, 24 Hours at +125
o
C Min
100% Interim Electrical Test 2 (Note 1)
100% Dynamic Burn-In Method 1015, 240 Hours at +125
o
C
or 180 Hours at +135
o
C
100% Interim Electrical Test 3 (Note 1)
100% Final Electrical Test
100% Fine and Gross Seal Method 1014
100% Radiographics Method 2012 (2 Views)
100% External Visual Method 2009
Group A (All Tests) Method 5005 (Class S)
Group B (Optional) Method 5005 (Class S) (Note 2)
Group D (Optional) Method 5005 (Class S) (Note 2)
CSI and/or GSI (Optional) (Note 2)
Data Package Generation (Note 3)
NOTES:
1. Failures from interim electrical tests 1 and 2 are combined for determining PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures com-
bined, PDA = 3% for subgroup 7 failures). Interim electrical tests 3 PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined,
PDA = 3% for subgroup 7 failures).
2. These steps are optional, and should be listed on the purchase order if required.
3. Data Package Contents:
Cover Sheet (P.O. Number, Customer Number, Lot Date Code, Intersil Number, Lot Number, Quantity).
Certificate of Conformance (as found on shipper).
Lot Serial Number Sheet (Good Unit(s) Serial Number and Lot Number).
Variables Data (All Read, Record, and delta operations).
Group A Attributes Data Summary.
Wafer Lot Acceptance Report (Method 5007) to include reproductions of SEM photos. NOTE: SEM photos to include percent of step coverage.
X-Ray Report and Film, including penetrometer measurements.
GAMMA Radiation Report with initial shipment of devices from the same wafer lot; containing a Cover Page, Disposition, RAD Dose,
Lot Number, Test Package, Spec Number(s), Test Equipment, etc. Irradiation Read and Record data will be on file at Intersil.
VS
INPUT
OUTPUT
VIH
VSS
VOH
VOL
TPLH
TPHL
VS
AC VOLTAGE LEVELS
PARAMETER
ACTS
UNITS
VCC
4.50
V
VIH
3.00
V
VS
1.30
V
VIL
0
V
GND
0
V
DUT
TEST
POINT
CL
RL
500
50pF
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| ACTS10MS | Radiation Hardened Triple Three-Input NAND Gate |
| ACTS10HMSR | CAP .022UF 50V 10% X7R 0805 |
| ACTS112D | Radiation Hardened Dual J-K Flip-Flop |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACTS10KMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple Three-Input NAND Gate |
| ACTS10MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple Three-Input NAND Gate |
| ACTS112D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual J-K Flip-Flop |
| ACTS112HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual J-K Flip-Flop |
| ACTS112K | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual J-K Flip-Flop |
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