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參數(shù)資料
| 型號(hào)： | ACTS10K |
| 廠商： | Intersil Corporation |
| 英文描述： | Radiation Hardened Triple Three-Input NAND Gate |
| 中文描述： | 輻射加固三三輸入與非門(mén) |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大小： | 112K |
| 代理商： | ACTS10K |
7
Spec Number
518823
ACTS10MS
D14.3
MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.200
-
5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.785
-
19.94
-
E
0.220
0.310
5.59
7.87
-
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
5
S1
0.005
-
0.13
-
6
S2
α
aaa
0.005
90
o
-
0.13
90
o
-
7
105
o
105
o
-
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2
N
14
14
8
Rev. 0 4/94
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
bbb
C A - B
S
c
Q
L
A
SEATING
PLANE
BASE
PLANE
D
S
S
-D-
-A-
-C-
e
A
-B-
aaa
C A - B
M
D
S
S
ccc
C A - B
M
D
S
S
D
E
S1
b2
b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
METAL
LEAD FINISH
e
A/2
S2
M
A
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
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PDF描述 |
|---|---|
| ACTS10MS | Radiation Hardened Triple Three-Input NAND Gate |
| ACTS10HMSR | CAP .022UF 50V 10% X7R 0805 |
| ACTS112D | Radiation Hardened Dual J-K Flip-Flop |
| ACTS112K | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACTS10KMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple Three-Input NAND Gate |
| ACTS10MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple Three-Input NAND Gate |
| ACTS112D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual J-K Flip-Flop |
| ACTS112HMSR | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual J-K Flip-Flop |
| ACTS112K | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual J-K Flip-Flop |
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