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參數(shù)資料
| 型號： | AD1835AASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC 2ADC/8DAC 24BIT 52-MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 立體聲音頻 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 8 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： | 105 / 108 |
| 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 105 / 108 |
| 電壓 - 電源，模擬： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，數(shù)字： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-QFP |
| 供應(yīng)商設(shè)備封裝： | 52-MQFP（10x10） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
REV. A
AD1835A
–21–
CASCADE MODE
Dual AD1835A Cascade
The AD1835A can be cascaded to an additional AD1835A
which, in addition to six external stereo ADCs, can be used to
create a 32-channel audio system with 16 inputs and 16 outputs.
The cascade is designed to connect to a SHARC DSP and oper-
ates in a time division multiplexing (TDM) format. Figure 16
shows the connection diagram for cascade operation. The digital
interface for both parts must be set to operate in Auxiliary 512
mode by programming ADC Control Register 2. AD1835A No. 1
is set as a master device by connecting the
M/S pin to DGND
and AD1835A No. 2 is set as a slave device by connecting the
M/S to ODVDD. Both devices should be run from the same
MCLK and
PD/RST signals to ensure that they are synchronized.
With Device 1 set as a master it will generate the frame-sync and
bit clock signals. These signals are sent to the SHARC and
Device 2, ensuring that both know when to send and receive data.
The cascade can be thought of as two 256 bit shift registers, one for
each device. At the beginning of a sample interval, the shift regis-
ters contain the ADC results from the previous sample interval.
The first shift register (Device 1) clocks data into the SHARC and
clocks in data from the second shift register (Device 2). While this
is happening, the SHARC is sending DAC data to the second shift
register. By the end of the sample interval, all 512 bits of ADC data
in the shift registers will have been clocked into the SHARC and
replaced by DAC data, which is subsequently written to the DACs.
Figure 17 shows the timing diagram for the cascade operation.
AUX ADC
(SLAVE)
ALRCLK
ABCLK
ASDATA
DSDATA
ALRCLK
ABCLK
ASDATA
DSDATA
AD1835A No. 1
(MASTER)
AD1835A No. 2
(SLAVE)
SHARC
(SLAVE)
DOUT
LRCLK
BCLK
AUX ADC
(SLAVE)
DOUT
LRCLK
BCLK
AUX ADC
(SLAVE)
DOUT
LRCLK
BCLK
AUX ADC
(SLAVE)
DOUT
LRCLK
BCLK
AUX ADC
(SLAVE)
DOUT
LRCLK
BCLK
AUX ADC
(SLAVE)
DOUT
LRCLK
BCLK
AU
X
BCLK
AU
X
L
RCLK
AU
X
D
A
T
A
1
AU
X
D
A
T
A
2
AU
X
D
A
T
A
3
AU
X
BCLK
AU
X
L
RCLK
AU
X
D
A
T
A
1
AU
X
D
A
T
A
2
AU
X
D
A
T
A
3
DRx
RFSx
RCLKx
TCLKx
DTx
TFSx
Figure 16. Dual AD1835A Cascade
AD1835A No. 1 DACs
L1
L2
L3
L4
R1
R2
R3
R4
AD1835A No. 2 DACs
L1
L2
L3
L4
R1
R2
R3
R4
TFSx/
RFSx
DTx
AD1835A No. 1 ADCs
L1
L2
L3
L4
R1
R2
R3
R4
AD1835A No. 2 ADCs
L1
L2
L3
L4
R1
R2
R3
R4
DRx
256 ABCLKs
MSB
MSB – 1
LSB
32 ABCLKs
ABCLK
DTx
MSB
MSB – 1
LSB
DRx
DON’T CARE
Figure 17. Dual AD1835A Cascade Timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1835AASZ-REEL | 功能描述:IC CODEC 2ADC/8DAC 24BIT 52MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| AD1835AS | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 8DAC 24-Bit 52-Pin MQFP 制造商:Analog Devices 功能描述:AUD CODEC 2ADC / 8DAC 24BIT 52MQFP - Trays 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE 2:8 CODEC - Bulk |
| AD1835AS-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 8DAC 24-Bit 52-Pin MQFP T/R |
| AD1836 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multichannel 96 kHz Codec |
| AD1836A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multichannel 96 kHz Codec |
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