2S Mode Auxiliary Mode " />
參數(shù)資料
型號: AD1835AASZ
廠商: Analog Devices Inc
文件頁數(shù): 8/24頁
文件大小: 0K
描述: IC CODEC 2ADC/8DAC 24BIT 52-MQFP
標(biāo)準(zhǔn)包裝: 1
類型: 立體聲音頻
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 8
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 105 / 108
動態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 105 / 108
電壓 - 電源,模擬: 4.5 V ~ 5.5 V
電壓 - 電源,數(shù)字: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 52-QFP
供應(yīng)商設(shè)備封裝: 52-MQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 776 (CN2011-ZH PDF)
REV. A
–16–
AD1835A
Table IV. Pin Function Changes in Auxiliary Mode
Pin Name
I
2S Mode
Auxiliary Mode
ASDATA (O)
I
2S Data Out, Internal ADC
TDM Data Out to SHARC.
DSDATA1 (I)
I
2S Data In, Internal DAC1
TDM Data In from SHARC.
DSDATA2 (I)/AAUXDATA1 (I)
I
2S Data In, Internal DAC2
AUX-I
2S Data In 1 (from External ADC).
DSDATA3 (I)/AAUXDATA2 (I)
I
2S Data In, Internal DAC3
AUX-I
2S Data In 2 (from External ADC).
DSDATA4 (I)/AAUXDATA3 (I)
I
2S Data In, Internal DAC4
AUX-I
2S Data In 3 (from External ADC).
ALRCLK (O)
LRCLK for ADC
TDM Frame Sync Out to SHARC (FSTDM).
ABCLK (O)
BCLK for ADC
TDM BCLK Out to SHARC.
DLRCLK (I)/AUXLRCLK(I/O)
LRCLK In/Out Internal DACs
AUX LRCLK In/Out. Driven by external LRCLK from ADC in
slave mode. In master mode, driven by MCLK/512.
DBCLK (I)/AUXBCLK(I/O)
BCLK In/Out Internal DACs
AUX BCLK In/Out. Driven by external BCLK from ADC
in slave mode. In master mode, driven by MCLK/8.
FSTDM
INTERNAL
ADC L1
AUX_ADC L2
AUX_ADC L3
AUX_ADC L4
INTERNAL
ADC R1
AUX_ADC R2
AUX_ADC R3
AUX_ADC R4
INTERNAL
DAC L1
INTERNAL
DAC L2
INTERNAL
DAC L3
INTERNAL
DAC R1
INTERNAL
DAC R2
INTERNAL
DAC R3
LEFT
RIGHT
I2S – MSB RIGHT
I2S – MSB LEFT
BCLK
TDM
ASDATA1
TDM (OUT)
ASDATA
DSDATA1
TDM (IN)
DSDATA1
AUX
LRCLK I2S
(FROM AUX ADC No. 1)
AUX
BCLK I2S
(FROM AUX ADC No. 1)
AAUXDATA1 (IN)
(FROM AUX ADC No. 1)
AAUXDATA2 (IN)
(FROM AUX ADC No. 2)
AAUXDATA3 (IN)
(FROM AUX ADC No. 3)
AUX BCLK FREQUENCY IS 64
FRAME RATE; TDM BCLK FREQUENCY IS 256
FRAME RATE.
TDM
I
N
TERFA
C
E
AUX
I
2
S
I
N
TERFACE
32
MSB TDM
I2S – MSB RIGHT
I2S – MSB LEFT
I2S – MSB RIGHT
I2S – MSB LEFT
INTERNAL
DAC L4
INTERNAL
DAC R4
MSB TDM
1ST
CH
1ST
CH
8TH
CH
8TH
CH
Figure 13. Auxiliary Mode Timing
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