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參數(shù)資料
| 型號： | AD1941YSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/36頁 |
| 文件大小： | 0K |
| 描述： | IC DSP AUDIO 16CHAN 28BIT 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應(yīng)用： | 車載系統(tǒng)，家庭影院，電視 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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AD1940/AD1941
Rev. B | Page 24 of
36
counter equals the capture count. The register select field
selections are shown in Table 23.
Table 23. Data Capture Output Register Select
Setting
Register
00
Multiplier X input (Mult_X_input)
01
Multiplier Y input (Mult_Y_input)
10
Multiplier-Accumulator Output (MAC_out)
11
Accumulator Feedback (Accum_fback)
The capture count and register select bits are set by writing to
one of the eight data capture registers at the following
register addresses:
2634: Control Port Data Capture Setup Register 0
2635: Control Port Data Capture Setup Register 1
2636: Control Port Data Capture Setup Register 2
2637: Control Port Data Capture Setup Register 3
2638: Control Port Data Capture Setup Register 4
2639: Control Port Data Capture Setup Register 5
2640: Digital Out Data Capture Setup Register 0
2641: Digital Out Data Capture Setup Register 1
The captured data is in 5.19 twos complement data format for
all eight register select fields. The four LSBs are truncated from
the internal 5.23 data-word.
The data that must be written to set up the data capture is a
concatenation of the 11-bit program count index with the 2-bit
register select field. The capture count and register select values
that correspond to the desired point to be monitored in the
signal processing flow can be found in a file output from the
program compiler. The capture registers can be accessed by
reading from locations 2634 to 2639 (for control port capture
registers). The format for reading and writing to the data
DSP CORE CONTROL REGISTER
The controls in this register set the operation of the AD1940/
AD1941’s DSP core. Bits 6 to 9 can be set to initiate a shutdown
of the core. The output is muted when this is performed, so it is
best to first assert the mute slew RAM bit (if slew RAM loca-
tions are used as volume controls in the program) to avoid a
click or pop when shutdown is asserted.
Slew RAM Muted (Bit 13)
This bit is set to 1 when the slew RAM mute operation has been
completed. This bit is read-only and is automatically cleared
by reading.
Mute Slew RAM, All Locations (Bit 12)
Setting this bit to 1 initiates a mute of all 64 slew RAM
locations. When reset to 0, all RAM locations return to their
previous state. This bit is only functional if slew RAM locations
are used in the custom program design. Keep in mind that the
AD1940/AD1941’s default program does not use any slew RAM
volume controls, so this bit has no effect in that case. The mute
operation is identical to writing all 0s to the data portion of the
target RAM, and therefore the time constant and linear/
exponential curve selection is determined by the bits that have
been previously written to the high bits of the target RAM.
Table 24. DSP Core Control Register (2642)
Register Bits
Function
15:14
Reserved
13
Slew RAM muted (read-only)
12
Mute slew RAM, all locations
11
Reserved, set to 0
10
Use serial out LRCLK for output latch
9
Clear internal registers to all 0s, active low
8
Force multiplier to 0
7
Inititalize data memory with 0s
6
Mute serial input port
5
Initiate safe transfer to target RAM
4
Initiate safe transfer to parameter RAM
3:2
Input serial port to sequencer sync
00 = LRCLK
01 = LRCLK/2
10 = LRCLK/4
11 = LRCLK/8
1:0
Program length
00 = 1536
01 = 768
10 = 384
11 = 192
Use Serial Out LRCLK for Output Latch (Bit 10)
Normally, data is transferred from the DSP core to the serial
output registers at the end of each program cycle. In some cases
(for example, when the output sample rate is set to some
multiple of the input sampling rate), it is desirable to transfer
the internal core data multiple times during a single input audio
sample period. Setting this bit to 1 allows the output LRCLK
signal to control this data transfer rather than the internal end-
of-sequence signal. Operation in this mode may require custom
assembly language coding in the ADI graphical tools.
Clear Registers to All Zeros (Bit 9)
Setting this bit to 0 sets the contents of the accumulators and
serial output registers to 0. Like the other register bits, this one
powers up to 0. This means the AD1940/AD1941 power up in
clear mode and do not pass a signal until a 1 is written to this
bit. This is intended to prevent noise from inadvertently
occurring during the power-up sequence.
Force Multiplier to Zero (Bit 8)
When this bit is set to 1, the input to the DSP multiplier is set to
0, which results in the multiplier output being 0. This control
bit is included for maximum flexibility and is normally not
used.
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