參數(shù)資料
型號(hào)： AD1941YSTZRL
廠商： Analog Devices Inc
文件頁數(shù)： 31/36頁
文件大小： 0K
描述： IC DSP AUDIO 16CHAN 28BIT 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： 車載系統(tǒng)，家庭影院，電視
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
AD1940/AD1941
Rev. B | Page 4 of
36
DIGITAL TIMING
VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C.
Table 4. Digital Timing1
Parameter
Mnemonic
Comments
Min
Max
Unit
MASTER CLOCK, SERIAL DATA PORTS, RESET
MCLK Period
tMP
512 fS mode
36
244
ns
MCLK Period
tMP
384 fS mode
48
366
ns
MCLK Period
tMP
256 fS mode
73
488
ns
MCLK Period
tMP
64 fS mode
291
1953
ns
MCLK Period
tMP
Bypass mode
12
ns
MCLK Duty Cycle
tMDC
Bypass mode
40
60
%
BCLK_IN LO Pulse Width
tBIL
4
ns
BCLK_IN HI Pulse Width
tBIH
2
ns
LRCLK_IN Setup
tLIS
To BCLK_IN rising
12
ns
LRCLK_IN Hold
tLIH
From BCLK_IN rising
0
ns
SDATA_INx Setup
tSIS
To BCLK_IN rising
3
ns
SDATA_INx Hold
tSIH
From BCLK_IN rising
2
ns
LRCLK_OUTx Setup
tLOS
Slave mode
2
ns
LRCLK_OUTx Hold
tLOH
Slave mode
2
ns
BCLK_OUTx Falling to LRCLK_OUTx
Timing Skew
tTS
2
ns
SDATA_OUTx Delay
tSODS
Slave mode, from
BCLK_OUTx falling
17
ns
SDATA_OUTx Delay
tSODM
Master mode, from
BCLK_OUTx falling
17
ns
RESETB LO Pulse Width
tRLPW
10
ns
SPI PORT (AD1940)
CCLK Pulse Width LO
tCCPL
1 × INTMCLK (14)2
ns
CCLK Pulse Width HI
tCCPH
1 × INTMCLK (14)2
ns
CLATCH Setup
tCLS
To CCLK rising
0
ns
CLATCH Hold
tCLH
From CCLK rising
2 × INTMCLK + 4 (32)2
ns
CLATCH Pulse Width HI
tCLPH
2 × INTMCLK (28)2
ns
CDATA Setup
tCDS
To CCLK rising
0
ns
CDATA Hold
tCDH
From CCLK rising
2 × INTMCLK + 2 (30)2
ns
COUT Delay
tCOD
From CCLK rising
4 × INTMCLK +18 (74)2
ns
I2C PORT (AD1941)
SCL Clock Frequency
fSCL
400
kHz
SCL Low
tSCLL
1.3
μs
SCL High
tSCLH
0.6
μs
Setup Time (Start Condition)
tSCS
Relevent for repeated start
condition
0.6
μs
Hold Time (Start Condition)
tSCH
First clock generated after
this period
0.6
μs
Setup Time (Stop Condition)
tSSH
0.6
μs
Data Setup Time
tDS
100
ns
SDA and SCL Rise Time
tSR
300
ns
SDA and SCL Fall Time
tSF
300
ns
Bus-Free Time
tBFT
Between stop and start
1.3
μs
1 All timing specifications are given for the default (I2S) states of the serial input control port and the serial output control ports. See Table 37.
2 These specifications are based on the internal master clock period in a specific application. In normal operation, the master clock runs at 1,536 × fs, so the internal
master clock at fs = 48 kHz has a 14 ns period. The values in parentheses are the timing values for fs = 48 kHz.
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