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| 型號： | AD5025BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC DUAL 12BIT SPI 14TSSOP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 系列： | nanoDAC™ |
| 設置時間： | 5.8µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 13.5mW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 14-TSSOP |
| 包裝： | 標準包裝 |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | * |
| 其它名稱： | AD5025BRUZ-REEL7DKR |
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Fully Accurate, 12-/14-/16-Bit, Dual, VOUT
nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP
AD5025/AD5045/AD5065
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2008 Analog Devices, Inc. All rights reserved.
FEATURES
Low power dual 12-/14-/16-bit DAC, ±1 LSB INL
Individual voltage reference pins
Rail-to-rail operation
4.5 V to 5.5 V power supply
Power-on reset to zero scale or midscale
Power down to 400 nA @ 5 V
3 power-down functions
Per channel power-down
Low glitch upon power-up
Hardware power-down lockout capability
Hardware LDAC with software LDAC override function
CLR function to programmable code
SDO daisy-chaining option
14-lead TSSOP
APPLICATIONS
Process controls
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5025/AD5045/AD5065 are low power, dual 12-/14-/16-bit
buffered voltage output nanoDAC DACs offering relative accuracy
specifications of ±1 LSB INL with individual reference pins, and
can operate from a single 4.5 V to 5.5 V supply. The AD5025/
AD5045/AD5065 also offer a differential accuracy specification of
±1 LSB. The parts use a versatile 3-wire, low power Schmitt
trigger serial interface that operates at clock rates up to 50 MHz
and is compatible with standard SPI, QSPI, MICROWIRE,
and DSP interface standards. The reference for the AD5025/
AD5045/AD5065 are supplied from an external pin and a refer-
ence buffer is provided on chip. The AD5025/AD5045/AD5065
incorporate a power-on reset circuit that ensures the DAC output
powers up zero scale or midscale and remains there until a valid
write takes place to the device. The AD5025/AD5045/AD5065
contain a power-down feature that reduces the current consump-
tion of the device to typically 400 nA at 5 V and provides software
selectable output loads while in power-down mode. The parts are
put into power-down mode over the serial interface. Total unad-
justed error for the parts is <2.5 mV. The parts exhibit very low
glitch on power-up. The outputs of all DACs can be updated
simultaneously using the LDAC function, with the added
functionality of user-selectable DAC channels to simultaneously
update. There is also an asynchronous CLR that clears all DACs
to a software-selectable code—0 V, midscale, or full scale. The
parts also feature a power-down lockout pin, PDL, which can be
used to prevent the DAC from entering power-down under any
circumstances over the serial interface.
PRODUCT HIGHLIGHTS
1.
Dual channel available in a 14-lead TSSOP package with
individual voltage reference pins.
2.
12-/14-/16-bit accurate, ±1 LSB INL.
3.
Low glitch on power-up.
4.
High speed serial interface with clock speeds up to 50 MHz.
5.
Three power-down modes available to the user.
6.
Reset to known output voltage (zero scale or midscale).
7.
Power-down lockout capability.
Table 1. Related Devices
Part No.
Description
Quad,16-bit buffered DAC, 16 LSB INL, TSSOP
Quad 16-bit nanoDAC, 1 LSB INL, TSSOP
16-bit nanoDAC, 1 LSB INL, MSOP
16-bit nanoDAC, 4 LSB INL, SOT-23
14-/16-bit nanoDAC, 1 LSB INL, SOT-23
FUNCTIONAL BLOCK DIAGRAM
INTERFACE
LOGIC
INPUT
REGISTER
DIN
LDAC
GND
VDD
LDAC
VREFB
SYNC
SCLK
AD5025/AD5045/AD5065
CLR
VOUTB
VOUTA
DAC
REGISTER
DAC A
INPUT
REGISTER
DAC
REGISTER
DAC B
BUFFER
VREFA
SDO
PDL
POR
POWER-DOWN
LOGIC
06
84
4-
0
01
Figure 1.
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