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參數(shù)資料
| 型號： | AD5025BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC DUAL 12BIT SPI 14TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | nanoDAC™ |
| 設(shè)置時(shí)間： | 5.8µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 13.5mW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | * |
| 其它名稱： | AD5025BRUZ-REEL7DKR |
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AD5025/AD5045/AD5065
Rev. 0 | Page 20 of 28
POWER-ON RESET AND SOFTWARE RESET
The AD5025/AD5045/AD5065 contain a power-on reset (POR)
circuit that controls the output voltage during power-up. By
connecting the POR pin low, the AD5025/AD5045/AD5065
output powers up to zero scale. Note that this is outside the
linear region of the DAC; by connecting the POR pin high, the
AD5025/AD5045/AD5065 output powers up to midscale. The
output remains powered up at this level until a valid write
where it is important to know the state of the output of the DAC
while it is in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code selected by the POR pin. Command 0111 is reserved
for this reset function (see Table 8).
POWER-DOWN MODES
The AD5025/AD5045/AD5065 contain four separate modes
of operation. Command 0100 is reserved for the power-down
function (see Table 8). These modes are software-programmable
by setting two bits, Bit DB9 and Bit DB8, in the input register (see
Table 12). Table 11 shows how the state of the bits corresponds
to the mode of operation of the device.
Table 11. Modes of Operation
DB9
DB8
Operating Mode
0
Normal operation, power-down modes
0
1
1 kΩ to GND
1
0
100 kΩ to GND
1
Three-state
When both Bit DB9 and Bit DB8 in the input register are set to 0,
the part works normally with its normal power consumption of
2.2 mA at 5 V. However, for the three power-down modes, the
supply current falls to 0.4 μV at 5 V. Not only does the supply
current fall, but the output stage is also internally switched from
the output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode. There are three
different options. The output is connected internally to GND
through either a 1 kΩ or a 100 kΩ resistor, or it is left open-
circuited (three-state). The output stage is illustrated in Figure 45.
RESISTOR
NETWORK
VOUT
DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
06
84
4-
01
1
Figure 45. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register are
unaffected when in power-down. The time to exit power-down
Either or both DACs (DAC A and DAC B) can be powered down
to the selected mode by setting the corresponding bits (DB3 and
DB0) to 1. See Table 12 for the contents of the input register
during power-down/power-up operation.
Any combination of DACs can be powered up by setting PD1 = 0
and PD0 = 0 (normal operation). The output powers up to the
value in the input register (LDAC low) or to the value in the
DAC register before powering down (LDAC high).
Table 12. 32-Bit Input Register Contents for Power-Up/Power-Down Function
MSB
LSB
DB31
to
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB10
to
DB19
DB9
DB8
DB4
to
DB7
DB3
DB2
DB1
DB0
X
0
1
0
X
PD1
PD0
X
DAC
B
DAC
B
DAC
A
DAC A
Don’t
cares
Command bits (C2 to C0)
Address bits (A3 to A0)—don’t
cares
Don’t
cares
Power-down
mode
Don’t
cares
Power-down/power-up channel
selection—set bits to 1 to select
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