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參數(shù)資料
| 型號： | AD5170BRMZ50-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 256POS 50K 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 35 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
AD5170
Rev. G | Page 5 of 24
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DYNAMIC CHARACTERISTICS13
–3 dB Bandwidth
BW_2.5k
Code = 0x80
4.8
MHz
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz
0.1
%
VW Settling Time
tS
VA = 5 V, VB = 0 V, ±1 LSB error
band
1
μs
Resistor Noise Voltage Density
eN_WB
RWB = 1.25 kΩ, f = 1 kHz
3.2
nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8 The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled
up to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without
pull-up resistors.
9 Different from operating power supply; power supply for OTP is used one time only.
10 Different from operating current; supply current for OTP lasts approximately 400 ms for use one time only.
11 See Figure 26 for the energy plot during OTP program.
12 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
13 All dynamic characteristics use VDD = 5 V.
ELECTRICAL CHARACTERISTICS: 10 kΩ, 50 kΩ, AND 100 kΩ
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, 40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
R-DNL
RWB, VA = no connect
1
±0.1
+1
LSB
R-INL
RWB, VA = no connect
2.5
±0.25
+2.5
LSB
Nominal Resistor Tolerance3
RAB
TA = 25°C
20
+20
%
Resistance Temperature Coefficient
(RAB/RAB)/T
35
ppm/°C
RWB (Wiper Resistance)
RWB
Code = 0x00, VDD = 5 V
160
200
Ω
DC CHARACTERISTICS—POTENTIOMETER DIVIDER
MODE (SPECIFICATIONS APPLY TO ALL VRs)
Differential Nonlinearity4
DNL
1
±0.1
+1
LSB
Integral Nonlinearity4
INL
1
±0.3
+1
LSB
Voltage Divider Temperature Coefficient
(VW/VW)/T
Code = 0x80
15
ppm/°C
Full-Scale Error
VWFSE
Code = 0xFF
2.5
1
0
LSB
Zero-Scale Error
VWZSE
Code = 0x00
0
1
2.5
LSB
RESISTOR TERMINALS
Voltage Range5
VA, VB, VW
GND
VDD
V
Capacitance A, Capacitance B6
CA, CB
f = 1 MHz, measured to GND,
code = 0x80
45
pF
CW
f = 1 MHz, measured to GND,
code = 0x80
60
pF
Shutdown Supply Current7
IA_SD
VDD = 5.5 V
0.01
1
μA
Common-Mode Leakage
ICM
VA = VB = VDD/2
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High (SDA and SCL)8
VIH
VDD = 5 V
0.7 VDD
VDD + 0.5
V
Input Logic Low (SDA and SCL)8
VIL
VDD = 5 V
0.5
+0.3 VDD
V
Input Logic High (AD0 and AD1)
VIH
VDD = 3 V
2.1
V
Input Logic Low (AD0 and AD1)
VIL
VDD = 3 V
0.6
V
Input Current
IIL
VIN = 0 V or 5 V
±1
μA
Input Capacitance6
CIL
5
pF
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