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參數(shù)資料
| 型號： | AD5170BRMZ50-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL POT 256POS 50K 10MSOP |
| 標準包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 35 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
AD5170
Rev. G | Page 6 of 24
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
POWER SUPPLIES
Power Supply Range
VDD RANGE
2.7
5.5
V
VDD_OTP
5.6
5.7
5.8
V
Supply Current
IDD
VIH = 5 V or VIL = 0 V
3.5
6
μA
IDD_OTP
VDD_OTP = 5 V, TA = 25°C
100
mA
Power Dissipation12
PDISS
VIH = 5 V or VIL = 0 V, VDD = 5 V
33
μW
Power Supply Sensitivity
PSS
VDD = 5 V ± 10%, code =
midscale
±0.02
±0.08
%/%
DYNAMIC CHARACTERISTICS13
–3 dB Bandwidth
BW
RAB = 10 kΩ, code = 0x80
600
kHz
RAB = 50 kΩ, code = 0x80
100
kHz
RAB = 100 kΩ, code = 0x80
40
kHz
Total Harmonic Distortion
THDW
VA =1 V rms, VB = 0 V, f = 1 kHz,
RAB = 10 kΩ
0.1
%
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)
tS
VA = 5 V, VB = 0 V, ±1 LSB error
band
2
μs
Resistor Noise Voltage Density
eN_WB
RWB = 5 kΩ, f = 1 kHz
9
nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8 The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up
to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-
up resistors.
9 Different from operating power supply, power supply OTP is used one time only.
10 Different from operating current, supply current for OTP lasts approximately 400 ms for use one time only.
11 See Figure 26 for the energy plot during OTP program.
12 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
13 All dynamic characteristics use VDD = 5 V.
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